Commit Graph

23 Commits

Author SHA1 Message Date
ba09e75c57 Multiplication implementation 2024-01-21 22:41:21 +01:00
ac3e34b2ef Don't warn on BLKSEQ 2024-01-21 22:41:21 +01:00
14cf222a6c Make ALU synchronous, generate and view traces 2024-01-21 22:41:18 +01:00
388c24ec78 Semantic names for tester 2024-01-17 14:46:35 +01:00
cdf37168cf Make verilator split carry array 2024-01-17 14:38:27 +01:00
4edeff9fe3 Include timing in tests 2024-01-17 14:38:14 +01:00
ef62808821 Automated tests 2024-01-17 13:58:25 +01:00
1f7f07b366 No overflow flag when not in addition nor subtraction mode 2024-01-17 13:58:14 +01:00
fb65ccc713 Move verilog-src to src, src/alu.v to src/alu/alu.v 2024-01-17 13:37:02 +01:00
69c367c344 Synthesizing 2024-01-17 12:25:46 +01:00
fdd0dd925a Change structure of tester 2024-01-17 12:25:06 +01:00
11c31c5baf Add multiplier function to ALU 2024-01-17 12:24:33 +01:00
d0dbbfee82 Don't warn on PINCONNECTEMPTY 2024-01-17 12:24:12 +01:00
87052a2f4e Implement bitwise operations 2024-01-13 00:16:32 +01:00
4203deb15b B6 -> B5 2024-01-12 23:08:26 +01:00
eb7cc73a80 Fix bug in carry_select_block 2024-01-12 23:08:18 +01:00
1f53f7e90f Pretty up the testing framework, split into files 2024-01-12 22:32:45 +01:00
82c6312f9d Update test_alu with a Tester class 2024-01-12 20:45:05 +01:00
49bad232bc Add -Wpedantic to CFLAGS 2024-01-12 20:44:16 +01:00
0adb95447e Remove old simulation 2024-01-12 18:42:01 +01:00
69dbe3b7c6 Rename project 2024-01-12 13:45:05 +01:00
e9b8d44104 Start work on ALU 2024-01-12 13:44:33 +01:00
8c126980a6 initial commit 2024-01-10 22:10:01 +01:00