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fpga-files
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Start work on ALU
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2024-01-12 13:44:33 +01:00 |
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simulation
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Remove old simulation
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2024-01-12 18:42:01 +01:00 |
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verilog-src
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Start work on ALU
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2024-01-12 13:44:33 +01:00 |
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.envrc
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initial commit
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2024-01-10 22:10:01 +01:00 |
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.gitignore
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initial commit
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2024-01-10 22:10:01 +01:00 |
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flake.lock
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initial commit
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2024-01-10 22:10:01 +01:00 |
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flake.nix
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Add -Wpedantic to CFLAGS
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2024-01-12 20:44:16 +01:00 |
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verilator.nix
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initial commit
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2024-01-10 22:10:01 +01:00 |
