Make verilator split carry array
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@ -22,7 +22,7 @@ module alu(
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wire [31:0] adder_out;
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begin
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begin : addsub
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wire addition = op == 3'b000;
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wire subtraction = op == 3'b001;
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wire [31:0] adder_B = subtraction ? ~B : B;
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@ -11,8 +11,8 @@ module carry_select_block#(
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// Case for Cin = 0
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wire [N-1:0] O_C0;
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wire [N-1:0] O_C1;
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wire [N:1] carry0;
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wire [N:1] carry1;
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wire carry0[N:1] /*verilator split_var*/;
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wire carry1[N:1] /*verilator split_var*/;
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fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
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fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);
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