From cdf37168cfcbc12dfc35f0dfa5f8264afffdd539 Mon Sep 17 00:00:00 2001
From: xenia <xenia.agda@gmail.com>
Date: Wed, 17 Jan 2024 14:38:27 +0100
Subject: [PATCH] Make verilator split carry array

---
 src/alu/alu.v                | 2 +-
 src/alu/carry_select_block.v | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/alu/alu.v b/src/alu/alu.v
index f326084..be2db09 100644
--- a/src/alu/alu.v
+++ b/src/alu/alu.v
@@ -22,7 +22,7 @@ module alu(
 
 wire [31:0] adder_out;
 
-begin
+begin : addsub
   wire addition = op == 3'b000;
   wire subtraction = op == 3'b001;
   wire [31:0] adder_B = subtraction ? ~B : B;
diff --git a/src/alu/carry_select_block.v b/src/alu/carry_select_block.v
index ca2cd0d..40eaa64 100644
--- a/src/alu/carry_select_block.v
+++ b/src/alu/carry_select_block.v
@@ -11,8 +11,8 @@ module carry_select_block#(
 // Case for Cin = 0
 wire [N-1:0] O_C0;
 wire [N-1:0] O_C1;
-wire [N:1] carry0;
-wire [N:1] carry1;
+wire carry0[N:1] /*verilator split_var*/;
+wire carry1[N:1] /*verilator split_var*/;
 
 fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
 fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);