xenia/fox32-hw
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19 Commits 1 Branch 0 Tags 88 KiB
C++ 66.3%
Verilog 19.3%
Nix 14.4%
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xenia cdf37168cf Make verilator split carry array
2024-01-17 14:38:27 +01:00
fpga-files Synthesizing 2024-01-17 12:25:46 +01:00
simulation Include timing in tests 2024-01-17 14:38:14 +01:00
src Make verilator split carry array 2024-01-17 14:38:27 +01:00
.envrc initial commit 2024-01-10 22:10:01 +01:00
.gitignore initial commit 2024-01-10 22:10:01 +01:00
flake.lock initial commit 2024-01-10 22:10:01 +01:00
flake.nix Move verilog-src to src, src/alu.v to src/alu/alu.v 2024-01-17 13:37:02 +01:00
verilator.nix initial commit 2024-01-10 22:10:01 +01:00