xenia ef62808821 Automated tests		2024-01-17 13:58:25 +01:00
fpga-files	Synthesizing	2024-01-17 12:25:46 +01:00
simulation	Automated tests	2024-01-17 13:58:25 +01:00
src	No overflow flag when not in addition nor subtraction mode	2024-01-17 13:58:14 +01:00
.envrc	initial commit	2024-01-10 22:10:01 +01:00
.gitignore	initial commit	2024-01-10 22:10:01 +01:00
flake.lock	initial commit	2024-01-10 22:10:01 +01:00
flake.nix	Move verilog-src to src, src/alu.v to src/alu/alu.v	2024-01-17 13:37:02 +01:00
verilator.nix	initial commit	2024-01-10 22:10:01 +01:00