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B6 -> B5

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xenia 2024-01-12 23:08:26 +01:00
parent eb7cc73a80
commit 4203deb15b
1 changed files with 1 additions and 1 deletions
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verilog-src/alu/carry_select_adder.v
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@ -24,6 +24,6 @@ carry_select_block#(6) B3 (A[23:18], B[23:18], Cout_17, O[23:18], Cout_23);
wire Cout_29;
carry_select_block#(6) B4 (A[29:24], B[29:24], Cout_23, O[29:24], Cout_29);
carry_select_block#(2) B6 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);
carry_select_block#(2) B5 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);
endmodule