diff --git a/verilog-src/alu/carry_select_adder.v b/verilog-src/alu/carry_select_adder.v
index 4215209..066f54e 100644
--- a/verilog-src/alu/carry_select_adder.v
+++ b/verilog-src/alu/carry_select_adder.v
@@ -24,6 +24,6 @@ carry_select_block#(6) B3 (A[23:18], B[23:18], Cout_17, O[23:18], Cout_23);
 wire Cout_29;
 carry_select_block#(6) B4 (A[29:24], B[29:24], Cout_23, O[29:24], Cout_29);
 
-carry_select_block#(2) B6 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);
+carry_select_block#(2) B5 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);
 
 endmodule