xenia/fox32-hw
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C++ 66.3%
Verilog 19.3%
Nix 14.4%
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xenia 69dbe3b7c6 Rename project
2024-01-12 13:45:05 +01:00
fpga-files Start work on ALU 2024-01-12 13:44:33 +01:00
simulation Start work on ALU 2024-01-12 13:44:33 +01:00
verilog-src Start work on ALU 2024-01-12 13:44:33 +01:00
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