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fpga-files
|
Synthesizing
|
2024-01-17 12:25:46 +01:00 |
|
simulation
|
Change structure of tester
|
2024-01-17 12:25:06 +01:00 |
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verilog-src
|
Synthesizing
|
2024-01-17 12:25:46 +01:00 |
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.envrc
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
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.gitignore
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initial commit
|
2024-01-10 22:10:01 +01:00 |
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flake.lock
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initial commit
|
2024-01-10 22:10:01 +01:00 |
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flake.nix
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Synthesizing
|
2024-01-17 12:25:46 +01:00 |
|
verilator.nix
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initial commit
|
2024-01-10 22:10:01 +01:00 |
