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ac3e34b2ef
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Don't warn on BLKSEQ
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2024-01-21 22:41:21 +01:00 |
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14cf222a6c
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Make ALU synchronous, generate and view traces
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2024-01-21 22:41:18 +01:00 |
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388c24ec78
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Semantic names for tester
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2024-01-17 14:46:35 +01:00 |
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cdf37168cf
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Make verilator split carry array
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2024-01-17 14:38:27 +01:00 |
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4edeff9fe3
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Include timing in tests
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2024-01-17 14:38:14 +01:00 |
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ef62808821
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Automated tests
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2024-01-17 13:58:25 +01:00 |
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1f7f07b366
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No overflow flag when not in addition nor subtraction mode
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2024-01-17 13:58:14 +01:00 |
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fb65ccc713
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Move verilog-src to src, src/alu.v to src/alu/alu.v
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2024-01-17 13:37:02 +01:00 |
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69c367c344
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Synthesizing
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2024-01-17 12:25:46 +01:00 |
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fdd0dd925a
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Change structure of tester
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2024-01-17 12:25:06 +01:00 |
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11c31c5baf
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Add multiplier function to ALU
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2024-01-17 12:24:33 +01:00 |
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d0dbbfee82
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Don't warn on PINCONNECTEMPTY
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2024-01-17 12:24:12 +01:00 |
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87052a2f4e
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Implement bitwise operations
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2024-01-13 00:16:32 +01:00 |
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4203deb15b
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B6 -> B5
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2024-01-12 23:08:26 +01:00 |
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eb7cc73a80
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Fix bug in carry_select_block
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2024-01-12 23:08:18 +01:00 |
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1f53f7e90f
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Pretty up the testing framework, split into files
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2024-01-12 22:32:45 +01:00 |
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82c6312f9d
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Update test_alu with a Tester class
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2024-01-12 20:45:05 +01:00 |
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49bad232bc
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Add -Wpedantic to CFLAGS
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2024-01-12 20:44:16 +01:00 |
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0adb95447e
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Remove old simulation
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2024-01-12 18:42:01 +01:00 |
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69dbe3b7c6
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Rename project
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2024-01-12 13:45:05 +01:00 |
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e9b8d44104
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Start work on ALU
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2024-01-12 13:44:33 +01:00 |
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8c126980a6
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initial commit
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2024-01-10 22:10:01 +01:00 |
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