Make verilator split carry array

simulation/tester.cpp

@@ -13,7 +13,8 @@ Tester::Tester(std::string test_name) :
     parent(),
     name(test_name),
     succeeded(0), failed(0),
-    detailed(true)
+    detailed(true),
+    started(std::chrono::steady_clock::now())
 {
     intro();
 }
@@ -22,7 +23,8 @@ Tester::Tester(Tester* tester_parent, std::string test_name) :
     parent(tester_parent),
     name(test_name),
     succeeded(0), failed(0),
-    detailed(false)
+    detailed(false),
+    started(std::chrono::steady_clock::now())
 {
     intro();
 }
@@ -31,7 +33,8 @@ Tester::Tester(Tester* tester_parent, std::string test_name, bool show_details)
     parent(tester_parent),
     name(test_name),
     succeeded(0), failed(0),
-    detailed(show_details)
+    detailed(show_details),
+    started(std::chrono::steady_clock::now())
 {
     intro();
 }
@@ -145,17 +148,45 @@ Tester::~Tester() {
 }
 
 void Tester::finish() {
+    std::chrono::duration<double> time_taken = std::chrono::steady_clock::now() - started;
+
+    double time_secs = time_taken.count();
+    double time_per_test_secs = time_secs / (succeeded + failed);
+    char time_s[20], time_per_s[20];
+    if (time_secs < 1e-6) {
+        snprintf(time_s, sizeof time_s, "%.1fns", time_secs * 1e9);
+    } else if (time_secs < 1e-3) {
+        snprintf(time_s, sizeof time_s, "%.1fµs", time_secs * 1e6);
+    } else if (time_secs < 1) {
+        snprintf(time_s, sizeof time_s, "%.1fms", time_secs * 1e3);
+    } else {
+        snprintf(time_s, sizeof time_s, "%.1fs", time_secs);
+    }
+
+    if (time_per_test_secs < 1e-6) {
+        snprintf(time_per_s, sizeof time_per_s, "%.1fns", time_per_test_secs * 1e9);
+    } else if (time_per_test_secs < 1e-3) {
+        snprintf(time_per_s, sizeof time_per_s, "%.1fµs", time_per_test_secs * 1e6);
+    } else if (time_per_test_secs < 1) {
+        snprintf(time_per_s, sizeof time_per_s, "%.1fms", time_per_test_secs * 1e3);
+    } else {
+        snprintf(time_per_s, sizeof time_per_s, "%.1fs", time_per_test_secs);
+    }
+
     char n_cases_s[10], n_succeeded_s[10], n_failed_s[10];
     snprintf(n_cases_s, sizeof n_cases_s, "%d", succeeded + failed);
     snprintf(n_succeeded_s, sizeof n_succeeded_s, "%d", succeeded);
     snprintf(n_failed_s, sizeof n_failed_s, "%d", failed);
+    bool printed = false;
     if (failed == 0) {
-        // printf("[ %s ] - %sall succeeded%s, out of %d total\n", name.c_str(), ANSI_GREEN.c_str(), ANSI_RESET.c_str(), succeeded + failed);
+        if (shown()) {
-        if (shown())
+            std::cout << prefix() << "=== " << ANSI_GREEN << "all succeeded" << ANSI_RESET << ", out of " << n_cases_s << " total";
-            std::cout << prefix() << "=== " << ANSI_GREEN << "all succeeded" << ANSI_RESET << ", out of " << n_cases_s << " total" << std::endl;
+            printed = true;
-    } else {
-        std::cout << prefix() << "=== " << ANSI_RED << n_failed_s << " failed" << ANSI_RESET << ", " << ANSI_GREEN << n_succeeded_s << " succeeded" << ANSI_RESET << " out of " << n_cases_s << " total" << std::endl;
-        // printf("[ %s ] - %s%d failed, %d succeeded%s, out of %d total\n", name.c_str(), ANSI_RED.c_str(), failed, succeeded, ANSI_RESET.c_str(), succeeded + failed);
         }
+    } else {
+        std::cout << prefix() << "=== " << ANSI_RED << n_failed_s << " failed" << ANSI_RESET << ", " << ANSI_GREEN << n_succeeded_s << " succeeded" << ANSI_RESET << " out of " << n_cases_s << " total";
+        printed = true;
+    }
+    if (printed)
+        std::cout << " (" << ANSI_YELLOW << time_s << ANSI_RESET << " total, " << ANSI_YELLOW << time_per_s << ANSI_RESET << " per test)" << std::endl;
 }
-

simulation/tester.hpp

@@ -35,6 +35,7 @@ class Tester {
         bool shown();
         std::string full_name();
         std::string prefix();
+        std::chrono::time_point<std::chrono::steady_clock> started;
 };
 
 #endif // tester_hpp_INCLUDED

src/alu/alu.v

@@ -22,7 +22,7 @@ module alu(
 
 wire [31:0] adder_out;
 
-begin
+begin : addsub
   wire addition = op == 3'b000;
   wire subtraction = op == 3'b001;
   wire [31:0] adder_B = subtraction ? ~B : B;

src/alu/carry_select_block.v

@@ -11,8 +11,8 @@ module carry_select_block#(
 // Case for Cin = 0
 wire [N-1:0] O_C0;
 wire [N-1:0] O_C1;
-wire [N:1] carry0;
+wire carry0[N:1] /*verilator split_var*/;
-wire [N:1] carry1;
+wire carry1[N:1] /*verilator split_var*/;
 
 fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
 fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);