254 lines
9.4 KiB
Markdown
254 lines
9.4 KiB
Markdown
# fox32 CPU
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This document aims to describe the CPU in the the fox32 architecture.
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Peripherals such as the disk controller are described in [io_bus.md](./io_bus.md).
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## Endianness
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All 16-bit or 32-bit values are stored in memory in little-endian order.
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## Registers
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The fox32 CPU has the following registers:
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- **r0-r31**: 32-bit general-purpose registers
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- **rsp**: current stack pointer
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- **resp**: exception stack pointer
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- **rfp**: frame pointer
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- **rip**: instruction pointer
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- condition flags, which are updated after some operations
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- **zero flag**
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- **carry flag**
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- other flags
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- enable use of exception stack pointer (**swap sp**)
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- **interrupt flag**, to enable interrupt handling
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- MMU state
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- **MMU enabled** flag
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- **page directory pointer**
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## External buses
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There are two kinds of external bus that the fox32 CPU can address:
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- **Memory**: Data is read from and written to memory with the `mov` instruction,
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instructions are fetched from memory.
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- **I/O bus**: Peripherals are connected to the I/O bus. Peripheral registers
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can be read using the `in` instruction and written using the `out` instruction.
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## Instruction encoding
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All instructions start with a 16-bit control word, which is optionally followed
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by a source operand, or by source and target operands, depending on the opcode.
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| bits | name | description
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|--------|--------|---------------------------------------------------
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| 1:0 | source | source operand type
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| 3:2 | target | target operand type
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| 6:4 | cond | condition code
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| 7 | --- | reserved, must be zero
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| 13:8 | opcode | operation code/type, e.g. `mov` or `add`
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| 15:14 | size | operation size, e.g. 32 bits
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NOTE: Although in the instruction encoding the source operand comes first,
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followed by the target operand, the order is reversed in the fox32 assembly
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language. The following lines are equivalent:
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```
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cmp r1, r20
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data.16 0x8700 data.8 20 data.8 1
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```
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### Operand types
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| value | description | size of operand | what's actually stored?
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|-------|-----------------------|------------------|--------------------------
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| 0 | register | 8 bits | register number
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| 1 | register pointer | 8 bits | register number
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| 2 | immediate | operation size | value
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| 3 | immediate pointer | 32 bits | pointer to memory location
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### Register numbers
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| value | register
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|-------|---------------------------------------------------------------------
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| 0-31 | r0-r31
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| 32 | rsp
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| 33 | resp
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| 34 | rfp
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### Condition codes
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| value | name | description
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|-------|-------------|-----------------------------------------------------
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| 0 | always | execute unconditionally
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| 1 | ifz | execute if zero flag is set
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| 2 | ifnz | execute if zero flag is not set
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| 3 | ifc/iflt | execute if carry flag is set
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| 4 | ifnc/ifgteq | execute if carry flag is not set
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| 5 | ifgt | execute if neither zero flag nor carry flag is set
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| 6 | iflteq | execute if zero flag or carry flag is set
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### Operation codes
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| value | name | operands | op sizes| description
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|-------|--------|----------|---------|-----------------------------------------------------
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| 0x00 | NOP | none | 8/16/32 | no operation
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| 0x01 | ADD | src+tgt | 8/16/32 | add
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| 0x02 | MUL | src+tgt | 8/16/32 | multiply (unsigned)
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| 0x03 | AND | src+tgt | 8/16/32 | bitwise AND
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| 0x04 | SLA | src+tgt | 8/16/32 | shift left
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| 0x05 | SRA | src+tgt | 8/16/32 | shift right arithmetic (with sign extension)
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| 0x06 | BSE | src+tgt | 8/16/32 | bit set
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| 0x07 | CMP | src+tgt | 8/16/32 | compare
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| 0x08 | JMP | src | 32 | absolute jump
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| 0x09 | RJMP | src | 32 | relative jump
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| 0x0A | PUSH | src | 8/16/32 | push value to stack
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| 0x0B | IN | src+tgt | 32 | get input from I/O bus
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| 0x0C | ISE | none | 32 | set interrupt enable flag
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| 0x0D | MSE | none | 32 | set MMU enable flag
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| 0x10 | HALT | none | 8/16/32 | halt CPU
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| 0x11 | INC | src | 8/16/32 | increment (add 1 << tgt in opcode encoding)
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| 0x13 | OR | src+tgt | 8/16/32 | bitwise OR
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| 0x14 | IMUL | src+tgt | 8/16/32 | multiply (signed)
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| 0x15 | SRL | src+tgt | 8/16/32 | shift right logical (with zero extension)
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| 0x16 | BCL | src+tgt | 8/16/32 | bit clear
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| 0x17 | MOV | src+tgt | 8/16/32 | move value
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| 0x18 | CALL | src | 32 | absolute call
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| 0x19 | RCALL | src | 32 | relative call
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| 0x1A | POP | src | 8/16/32 | pop value from stack
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| 0x1B | OUT | src+tgt | 32 | output on I/O bus
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| 0x1C | ICL | none | 32 | clear interrupt enable flag
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| 0x1D | MCL | none | 32 | clear MMU enable flag
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| 0x20 | BRK | none | 8/16/32 | debug breakpoint
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| 0x21 | SUB | src+tgt | 8/16/32 | subtract
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| 0x22 | DIV | src+tgt | 8/16/32 | divide (unsigned)
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| 0x23 | XOR | src+tgt | 8/16/32 | bitwise XOR
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| 0x24 | ROL | src+tgt | 8/16/32 | rotate left
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| 0x25 | ROR | src+tgt | 8/16/32 | rotate right
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| 0x26 | BTS | src+tgt | 8/16/32 | test if bit set
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| 0x27 | MOVZ | src+tgt | 8/16/32 | move value and clear upper bits in target register
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| 0x28 | LOOP | src | 32 | absolute loop
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| 0x29 | RLOOP | src | 32 | relative loop
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| 0x2A | RET | none | 32 | return from function
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| 0x2C | INT | src | 32 | raise interrupt
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| 0x2D | TLB | src | 32 | flush TLB and set page directory pointer
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| 0x31 | DEC | src | 8/16/32 | decrement (subtract 1 << tgt in opcode encoding)
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| 0x32 | REM | src+tgt | 8/16/32 | calculate remainder of division (unsigned)
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| 0x33 | NOT | src | 8/16/32 | bitwise NOT
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| 0x34 | IDIV | src+tgt | 8/16/32 | divide (signed)
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| 0x35 | IREM | src+tgt | 8/16/32 | remainder (signed)
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| 0x39 | RTA | src+tgt | 32 | calculate address relative to instruction pointer
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| 0x3A | RETI | none | 32 | return from interrupt
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| 0x3D | FLP | src | 32 | flush page from TLB
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### Operation sizes
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| value | description
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|-------|--------------------------------------------------------------
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| 0 | byte (8 bits)
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| 1 | half (16 bits)
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| 2 | word (32 bits)
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| 3 | reserved
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For SLA, SRA, SRL, ROR, ROL, BCL, BSE, BTS, src immediates are fixed to 8 bits
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## Interrupts and Exceptions
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Interrupts indicate asynchronous hardware events (such as VSYNC) or execution
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of the `int` instruction, while exceptions indicate various synchronous errors.
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There are 0x100 interrupt vectors and 5 exception vectors. Interrupt vectors
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are at 0x000 to 0x3FC, and exception vectors at 0x400 to 0x410. These memory
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locations simply store the address of the interrupt/exception handler,
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or 0x0 when no handler has been installed.
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(TODO: what should the hardware do when a handler is missing?)
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| type | vector | description
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|-----------|----------|-------------------------------------------
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| interrupt | 0 - 0xF0 | free for software use
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| interrupt | 0xFB | audio channel 3 refill
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| interrupt | 0xFC | audio channel 2 refill
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| interrupt | 0xFD | audio channel 1 refill
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| interrupt | 0xFE | audio channel 0 refill
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| interrupt | 0xFF | display VSYNC
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| exception | 0x00 | divide by zero
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| exception | 0x01 | invalid opcode
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| exception | 0x02 | page fault during read
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| exception | 0x03 | page fault during write
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| exception | 0x04 | breakpoint
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Upon interrupt/exception entry, the CPU performs the following operations:
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- read handler address from vector
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- if *swap sp* is enabled:
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- switch to the exception stack pointer, and push the old stack pointer
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- push current instruction pointer
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- push flags (8 bits)
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- push interrupt vector (0x00-0xff) or exception operand
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- clear interrupt flag and *swap sp* flag
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- jump to handler
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Interrupt/exception handlers are exited through the `reti` instruction, which
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performs the following operations:
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- pop and restore flags
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- pop instruction pointer
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- if *swap sp* flag is set, pop stack pointer
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The flags are stored in the following format:
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| bit | description
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|--------|-----------------------------------------------
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| 0 | zero flag
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| 1 | carry flag
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| 2 | interrupt flag
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| 3 | *swap sp* flag
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## MMU
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If the MMU is enabled, two-level page tables are used to translate virtual
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addresses to physical addresses.
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The address of the page directory can be set using the `tlb` instruction.
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| virtual address bits | purpose
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|-----------------------|--------------------------------------------------
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| 11:0 | lowest 12 bits of physical address
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| 21:12 | page table index
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| 31:22 | page directory index
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Page directories and page tables are arrays of 1024 elements of the following format:
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| bits | bit mask ts | purpose
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|-------|---------------|--------------------------------------------------
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| 31:12 | 0xfffff000 | address of page table or page
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| 1 | 0x00000002 | page is writable
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| 0 | 0x00000001 | page table or page is present
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A page table walk is performed as follows:
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- read page directory entry at page directory index in page directory
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- abort if page table is not present
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- read page table entry at page table index in page table
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- abort of page is not present
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- use physical page address and writability information from page table entry
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