updated docs
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@ -162,6 +162,7 @@ data.16 0x8700 data.8 20 data.8 1
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| 2 | word (32 bits)
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| 3 | reserved
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For SLA, SRA, SRL, ROR, ROL, BCL, BSE, BTS, src immediates are fixed to 8 bits
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## Interrupts and Exceptions
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@ -1,7 +1,7 @@
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# Encoding
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```
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size instr . cond dest src <src> <dest>
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xx xxxxxx 0 xxx xx xx <8,16,32 bits> <8,16,32 bits>
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size instr off cond dest src <src> <srcoff> <dest> <dstoff>
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xx xxxxxx x xxx xx xx <8,16,32 bits> <8 bits> <8,16,32 bits> <8 bits>
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```
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@ -49,3 +49,6 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
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| 0b01 | register (pointer) |
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| 0b10 | immediate |
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| 0b11 | immediate (pointer) |
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# Register Pointer Offset
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The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate. This immediate is added to the value of the register before derefencing.
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@ -8,8 +8,8 @@ description of the fox32 CPU and instruction encoding details, see [cpu.md](./cp
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### ADD: add
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### SUB: subtract
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### INC: increment (add 1)
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### DEC: decrement (subtract 1)
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### INC: increment (add 1/2/4/8)
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### DEC: decrement (subtract 1/2/4/8)
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### CMP: compare
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### AND: bitwise AND
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### OR: bitwise OR
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