From fac2865075fe2c68ecd88ade1aac1378f6ff021c Mon Sep 17 00:00:00 2001 From: eiowlta Date: Sun, 23 Jul 2023 14:44:51 +0300 Subject: [PATCH] updated docs --- docs/cpu.md | 1 + docs/encoding.md | 7 +++++-- docs/instructions.md | 4 ++-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/docs/cpu.md b/docs/cpu.md index 69d7c6a..d857743 100644 --- a/docs/cpu.md +++ b/docs/cpu.md @@ -162,6 +162,7 @@ data.16 0x8700 data.8 20 data.8 1 | 2 | word (32 bits) | 3 | reserved +For SLA, SRA, SRL, ROR, ROL, BCL, BSE, BTS, src immediates are fixed to 8 bits ## Interrupts and Exceptions diff --git a/docs/encoding.md b/docs/encoding.md index 7fe2cc0..bc5e1ad 100644 --- a/docs/encoding.md +++ b/docs/encoding.md @@ -1,7 +1,7 @@ # Encoding ``` -size instr . cond dest src -xx xxxxxx 0 xxx xx xx <8,16,32 bits> <8,16,32 bits> +size instr off cond dest src +xx xxxxxx x xxx xx xx <8,16,32 bits> <8 bits> <8,16,32 bits> <8 bits> ``` @@ -49,3 +49,6 @@ If the instruction doesn't allow variable sizes or a size was not specified, set | 0b01 | register (pointer) | | 0b10 | immediate | | 0b11 | immediate (pointer) | + +# Register Pointer Offset +The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate. This immediate is added to the value of the register before derefencing. \ No newline at end of file diff --git a/docs/instructions.md b/docs/instructions.md index 5cbd730..5c41760 100644 --- a/docs/instructions.md +++ b/docs/instructions.md @@ -8,8 +8,8 @@ description of the fox32 CPU and instruction encoding details, see [cpu.md](./cp ### ADD: add ### SUB: subtract -### INC: increment (add 1) -### DEC: decrement (subtract 1) +### INC: increment (add 1/2/4/8) +### DEC: decrement (subtract 1/2/4/8) ### CMP: compare ### AND: bitwise AND ### OR: bitwise OR