18 lines
385 B
Verilog
18 lines
385 B
Verilog
// Dummy module for connecting ALU and similar things, without having to break all inputs and outputs into separate pads
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module topmost(input clk, input [2:0] op, output xor_reduce);
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reg [31:0] A;
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reg [31:0] B;
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wire [31:0] O;
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alu alu(.A(A), .B(B), .op(op), .O(O), .Fflow(), .Fzero());
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always @(posedge clk) begin
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A <= A + 1;
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B <= B + 3;
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end
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assign xor_reduce = ^ O;
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endmodule
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