fox32-hw/verilog-src/topmost.v

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2024-01-17 12:25:36 +01:00
// Dummy module for connecting ALU and similar things, without having to break all inputs and outputs into separate pads
module topmost(input clk, input [2:0] op, output xor_reduce);
reg [31:0] A;
reg [31:0] B;
wire [31:0] O;
alu alu(.A(A), .B(B), .op(op), .O(O), .Fflow(), .Fzero());
always @(posedge clk) begin
A <= A + 1;
B <= B + 3;
end
assign xor_reduce = ^ O;
endmodule