Synthesizing

flake.nix

@@ -10,8 +10,9 @@
       let pkgs = nixpkgs.legacyPackages.${sys};
 
           verilator = import ./verilator.nix pkgs ;
+          yosys = pkgs.yosys;
 
-          vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -CFLAGS "-Wpedantic -std=c++20"'';
+          vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -Wno-PINCONNECTEMPTY -CFLAGS "-Wpedantic -std=c++20"'';
 
           verilate-src = cmd: ''
             cp -r ${./verilog-src} ./verilog-src
@@ -31,8 +32,17 @@
             mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim"
           '';
 
-          deps = with pkgs; [
+          alu-synth = pkgs.runCommandCC "alu-synth" {} ''
-            yosys nextpnrWithGui icestorm verilator
+            mkdir -p "$out"
+            find ${./verilog-src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
+          '';
+
+          alu-synth-view = pkgs.writeScriptBin "alu-synth-view" ''
+            ${pkgs.nextpnrWithGui}/bin/nextpnr-ice40 --up5k --package sg48 --pcf ${./fpga-files/rot.pcf} --json ${alu-synth}/synth.json --gui
+          '';
+
+          deps = [
+            yosys pkgs.nextpnrWithGui pkgs.icestorm verilator
           ];
       in rec {
         packages.verilator = verilator;
@@ -40,6 +50,9 @@
         packages.lint = lint;
 
         packages.alu-sim = alu-sim;
+        packages.alu-synth = alu-synth;
+        packages.alu-synth-view = alu-synth-view;
+
         devShells.default = pkgs.mkShell {
           packages = deps;
         };

fpga-files/rot.pcf

@@ -1,5 +1,5 @@
-set_io D0 23
+set_io clk 39
-set_io D1 27
+set_io op[0] 40
-set_io D2 21
+set_io op[1] 41
-set_io D3 25
+set_io op[2] 42
-set_io clk 35
+set_io xor_reduce 10

simulation/test_alu.cpp

@@ -1,6 +1,53 @@
 #include "Valu.h"
 #include "verilated.h"
 #include "tester.hpp"
+#include <stdint.h>
+
+struct alu_testcase {
+    std::string name;
+    // Inputs
+    uint32_t A, B;
+    uint8_t op;
+
+    // Outputs
+    uint32_t O;
+    std::optional<bool> overflow, zero;
+
+    std::optional<unsigned int> max_cycles;
+};
+
+void test_op(Valu *valu, Tester *tester, alu_testcase test) {
+    Tester subtester(tester, test.name);
+
+    // assign inputs
+    valu->op = test.op;
+    valu->A = test.A;
+    valu->B = test.B;
+
+    valu->eval();
+
+    char o_name[100];
+    if (test.O < 0x100)
+        snprintf(o_name, sizeof o_name, "O == 0x%02x", test.O);
+    if (test.O < 0x10000)
+        snprintf(o_name, sizeof o_name, "O == 0x%04x", test.O);
+    else
+        snprintf(o_name, sizeof o_name, "O == 0x%08x", test.O);
+    subtester.assert_eq(o_name, valu->O, test.O);
+
+    if (test.overflow.has_value()) {
+        if (*test.overflow)
+            subtester.assert_eq("overflow flag set", valu->Fflow, 1);
+        else
+            subtester.assert_eq("no overflow flag", valu->Fflow, 0);
+    }
+    if (test.zero.has_value()) {
+        if (*test.zero)
+            subtester.assert_eq("zero flag set", valu->Fzero, 1);
+        else
+            subtester.assert_eq("no zero flag", valu->Fzero, 0);
+    }
+}
 
 int main(int argc, char **argv) {
     VerilatedContext *vctx = new VerilatedContext;
@@ -8,141 +55,114 @@ int main(int argc, char **argv) {
 
     Tester alu_t("alu");
     {
-        Tester add_t(&alu_t, "add");
+        Tester add_t(&alu_t, "add", true);
 
-        {
+        test_op(valu, &add_t, {
-            Tester add_case(&add_t, "0x2137+0x1234");
+            .name = "0x2137+0x1234",
-            valu->op = 0b000;
+            .A = 0x2137, .B = 0x1234, .op = 0b000,
-            valu->A = 0x2137;
+            .O = 0x336b, .overflow = false,
-            valu->B = 0x1234;
+        });
-            valu->eval();
+
-            add_case.assert_eq("O == 0x336b", valu->O, 0x336b);
+        test_op(valu, &add_t, {
-            add_case.assert_eq("no overflow", valu->Fflow, 0x0);
+            .name = "0x09+0x10",
-            add_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+            .A = 0x09, .B = 0x10, .op = 0b000,
+            .O = 0x19, .overflow = false,
+        });
+
+        test_op(valu, &add_t, {
+            .name = "0x5555+0x5555",
+            .A = 0x5555, .B = 0x5555, .op = 0b000,
+            .O = 0xaaaa, .overflow = false,
+        });
+
+        test_op(valu, &add_t, {
+            .name = "0xfffffffe+0x1",
+            .A = 0xfffffffe, .B = 0x1, .op = 0b000,
+            .O = 0xffffffff, .overflow = false, .zero = false,
+        });
+        test_op(valu, &add_t, {
+            .name = "0xffffffff+0x1",
+            .A = 0xffffffff, .B = 0x1, .op = 0b000,
+            .O = 0x0, .overflow = true, .zero = true,
+        });
+        test_op(valu, &add_t, {
+            .name = "0xffffffff+0x2",
+            .A = 0xffffffff, .B = 0x2, .op = 0b000,
+            .O = 0x1, .overflow = true, .zero = false,
+        });
+        test_op(valu, &add_t, {
+            .name = "0x0+0x0",
+            .A = 0x0, .B = 0x0, .op = 0b000,
+            .O = 0x0, .overflow = false, .zero = true,
+        });
     }
 
     {
-            Tester add_case(&add_t, "0x9+0x10");
+        Tester sub_t(&alu_t, "sub", true);
-            valu->op = 0b000;
+
-            valu->A = 0x9;
+        test_op(valu, &sub_t, {
-            valu->B = 0x10;
+            .name = "0x2137-0x0420",
-            valu->eval();
+            .A = 0x2137, .B = 0x0420, .op = 0b001,
-            add_case.assert_eq("O == 0x19", valu->O, 0x19);
+            .O = 0x1d17, .overflow = false,
-            add_case.assert_eq("no overflow", valu->Fflow, 0x0);
+        });
-            add_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+
+        test_op(valu, &sub_t, {
+            .name = "0x0-0x1",
+            .A = 0x0, .B = 0x1, .op = 0b001,
+            .O = 0xffffffff, .overflow = true,
+        });
+
+        test_op(valu, &sub_t, {
+            .name = "0x100-0x0200",
+            .A = 0x100, .B = 0x200, .op = 0b001,
+            .O = 0xffffff00, .overflow = true,
+        });
+
+        test_op(valu, &sub_t, {
+            .name = "0x21-0x9",
+            .A = 0x21, .B = 0x9, .op = 0b001,
+            .O = 0x18, .overflow = false, .zero = false,
+        });
+
+        test_op(valu, &sub_t, {
+            .name = "0x20-0x20",
+            .A = 0x20, .B = 0x20, .op = 0b001,
+            .O = 0x0, .overflow = false, .zero = true,
+        });
     }
 
     {
-            Tester add_case(&add_t, "0x5555+0x5555");
+        Tester bitwise_t(&alu_t, "bitwise", true);
-            valu->op = 0b000;
-            valu->A = 0x5555;
-            valu->B = 0x5555;
-            valu->eval();
-            add_case.assert_eq("O == 0xaaaa", valu->O, 0xaaaa);
-            add_case.assert_eq("no overflow", valu->Fflow, 0x0);
-            add_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
-
-        {
-            Tester add_case(&add_t, "0xffffffff+0x1");
-            valu->op = 0b000;
-            valu->A = 0xffffffff;
-            valu->B = 0x1;
-            valu->eval();
-            add_case.assert_eq("O == 0x0", valu->O, 0x0);
-            add_case.assert_eq("has overflow", valu->Fflow, 0x1);
-            add_case.assert_eq("has Fzero", valu->Fzero, 0x1);
-        }
-    }
-
-    {
-        Tester sub_t(&alu_t, "sub");
-
-        {
-            Tester sub_case(&sub_t, "0x2137-0x0420");
-            valu->op = 0b001;
-            valu->A = 0x2137;
-            valu->B = 0x0420;
-            valu->eval();
-            sub_case.assert_eq("O == 0x1d17", valu->O, 0x1d17);
-            sub_case.assert_eq("no underflow", valu->Fflow, 0x0);
-            sub_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
-
-        {
-            Tester sub_case(&sub_t, "0x100-0x200");
-            valu->op = 0b001;
-            valu->A = 0x100;
-            valu->B = 0x200;
-            valu->eval();
-            sub_case.assert_eq("O == 0xffffff00", valu->O, 0xffffff00);
-            sub_case.assert_eq("has underflow", valu->Fflow, 0x1);
-            sub_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
-
-        {
-            Tester sub_case(&sub_t, "0x0-0x1");
-            valu->op = 0b001;
-            valu->A = 0x0;
-            valu->B = 0x1;
-            valu->eval();
-            sub_case.assert_eq("O == 0xffffffff", valu->O, 0xffffffff);
-            sub_case.assert_eq("has underflow", valu->Fflow, 0x1);
-            sub_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
-
-        {
-            Tester sub_case(&sub_t, "0x20-0x20");
-            valu->op = 0b001;
-            valu->A = 0x20;
-            valu->B = 0x20;
-            valu->eval();
-            sub_case.assert_eq("O == 0x0", valu->O, 0x0);
-            sub_case.assert_eq("no underflow", valu->Fflow, 0x0);
-            sub_case.assert_eq("has Fzero", valu->Fzero, 0x1);
-        }
-    }
-
-    {
-        Tester bitwise_t(&alu_t, "bitwise");
         // 0x3 = 0b0011, 0x5 = 0b0101
-        {
-            Tester and_case(&bitwise_t, "0x3&0x5");
-            valu->op = 0b100;
-            valu->A = 0x3;
-            valu->B = 0x5;
-            valu->eval();
-            and_case.assert_eq("O == 0x1", valu->O, 0x1);
-            and_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
 
-        {
+        test_op(valu, &bitwise_t, {
-            Tester or_case(&bitwise_t, "0x3|0x5");
+            .name = "0x3&0x5",
-            valu->op = 0b101;
+            .A = 0x3, .B = 0x5, .op = 0b100,
-            valu->A = 0x3;
+            .O = 0x1, .zero = false,
-            valu->B = 0x5;
+        });
-            valu->eval();
-            or_case.assert_eq("O == 0x7", valu->O, 0x7);
-            or_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
 
-        {
+        test_op(valu, &bitwise_t, {
-            Tester xor_case(&bitwise_t, "0x3^0x5");
+            .name = "0x3|0x5",
-            valu->op = 0b110;
+            .A = 0x3, .B = 0x5, .op = 0b101,
-            valu->A = 0x3;
+            .O = 0x7, .zero = false,
-            valu->B = 0x5;
+        });
-            valu->eval();
-            xor_case.assert_eq("O == 0x6", valu->O, 0x6);
-            xor_case.assert_eq("no Fzero", valu->Fzero, 0x0);
-        }
 
-        {
+        test_op(valu, &bitwise_t, {
-            Tester xor_case(&bitwise_t, "~0xa5a5a5a5");
+            .name = "0x3^0x5",
-            valu->op = 0b111;
+            .A = 0x3, .B = 0x5, .op = 0b110,
-            valu->A = 0xa5a5a5a5;
+            .O = 0x6, .zero = false,
-            valu->eval();
+        });
-            xor_case.assert_eq("O == 0x5a5a5a5a", valu->O, 0x5a5a5a5a);
+
-            xor_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        test_op(valu, &bitwise_t, {
-        }
+            .name = "~0xa5a5a5a5",
+            .A = 0xa5a5a5a5, .B = 0x0, .op = 0b111,
+            .O = 0x5a5a5a5a, .zero = false,
+        });
+
+        test_op(valu, &bitwise_t, {
+            .name = "~0xffffffff",
+            .A = 0xffffffff, .B = 0x0, .op = 0b111,
+            .O = 0x0, .zero = true,
+        });
     }
 }

simulation/tester.cpp

@@ -9,6 +9,33 @@ const std::string ANSI_GREEN = "\033[38;5;2m";
 const std::string ANSI_RED = "\033[38;5;1m";
 const std::string ANSI_YELLOW = "\033[38;5;11m";
 
+Tester::Tester(std::string test_name) :
+    parent(),
+    name(test_name),
+    succeeded(0), failed(0),
+    detailed(true)
+{
+    intro();
+}
+
+Tester::Tester(Tester* tester_parent, std::string test_name) :
+    parent(tester_parent),
+    name(test_name),
+    succeeded(0), failed(0),
+    detailed(false)
+{
+    intro();
+}
+
+Tester::Tester(Tester* tester_parent, std::string test_name, bool show_details) :
+    parent(tester_parent),
+    name(test_name),
+    succeeded(0), failed(0),
+    detailed(show_details)
+{
+    intro();
+}
+
 int Tester::depth() {
     int depth = 0;
     for (std::optional<Tester*> at = this; at.has_value(); at = (*at)->parent) {
@@ -65,35 +92,48 @@ std::string Tester::prefix() {
 }
 
 void Tester::intro() {
+    if (shown())
         std::cout << prefix() << "=== " << ANSI_YELLOW << "start" << ANSI_RESET << std::endl;
 }
 
-Tester::Tester(std::string test_name) :
+bool name_show_overwritten(std::string name) {
-    parent(),
+    char *shown_c = std::getenv("SHOW_CASE");
-    name(test_name),
+    if (shown_c == NULL)
-    succeeded(0), failed(0)
+        return false;
-{
+    std::string shown(shown_c);
-    intro();
+
+    shown.push_back(' ');
+    shown.insert(0, " ");
+
+    name.push_back(' ');
+    name.insert(0, " ");
+
+    return shown.find(name) != std::string::npos;
 }
 
-Tester::Tester(Tester* tester_parent, std::string test_name) :
+bool Tester::shown() {
-    parent(tester_parent),
+    for (std::optional<Tester*> at = this; at.has_value(); at = (*at)->parent) {
-    name(test_name),
+        if (name_show_overwritten((*at)->name))
-    succeeded(0), failed(0)
+            return true;
-{
+    }
-    intro();
+
+    for (std::optional<Tester*> at = this; at.has_value(); at = (*at)->parent) {
+        if (!(*at)->detailed)
+            return false;
+    }
+    return true;
 }
 
 void Tester::assert_eq_str(std::string test_name, bool correct, std::string got_s, std::string expected_s) {
-    std::cout << prefix() << "- " << test_name;
     if (correct) {
-        std::cout << " " << ANSI_GREEN << "succeded" << ANSI_RESET << std::endl;
+        if (shown()) {
+            std::cout << prefix() << ANSI_GREEN << "✓ " << ANSI_RESET << test_name << ANSI_RESET << std::endl;
+        }
         for (std::optional<Tester*> at = this; at.has_value(); at = (*at)->parent) {
             (*at)->succeeded++;
         }
     } else {
-
+        std::cout << prefix() << ANSI_RED << "✗ " << ANSI_RESET << test_name << " - " << ANSI_RED << "got " << got_s << ", expected " << expected_s << ANSI_RESET << std::endl;
-        std::cout << " " << ANSI_RED << "failed - got " << got_s << ", expected " << expected_s << ANSI_RESET << std::endl;
         for (std::optional<Tester*> at = this; at.has_value(); at = (*at)->parent) {
             (*at)->failed++;
         }
@@ -111,6 +151,7 @@ void Tester::finish() {
     snprintf(n_failed_s, sizeof n_failed_s, "%d", failed);
     if (failed == 0) {
         // printf("[ %s ] - %sall succeeded%s, out of %d total\n", name.c_str(), ANSI_GREEN.c_str(), ANSI_RESET.c_str(), succeeded + failed);
+        if (shown())
             std::cout << prefix() << "=== " << ANSI_GREEN << "all succeeded" << ANSI_RESET << ", out of " << n_cases_s << " total" << std::endl;
     } else {
         std::cout << prefix() << "=== " << ANSI_RED << n_failed_s << " failed" << ANSI_RESET << ", " << ANSI_GREEN << n_succeeded_s << " succeeded" << ANSI_RESET << " out of " << n_cases_s << " total" << std::endl;

simulation/tester.hpp

@@ -7,6 +7,7 @@ class Tester {
         Tester(std::string test_name);
 
         Tester(Tester* tester_parent, std::string test_name);
+        Tester(Tester* tester_parent, std::string test_name, bool show_details);
 
         template<typename T, typename U>
         void assert_eq(std::string test_name, T got, U expected) {
@@ -28,8 +29,10 @@ class Tester {
         std::optional<Tester*> parent;
         std::string name;
         int succeeded, failed;
+        bool detailed;
 
         int depth();
+        bool shown();
         std::string full_name();
         std::string prefix();
 };

verilog-src/alu.v

@@ -3,7 +3,8 @@
   OP is the operation to perform:
     000 = add
     001 = sub
-    010 = mul
+    010 = mul_lo
+    011 = mul_hi
     (011)
     100 = and
     101 = or
@@ -30,9 +31,15 @@ begin
   assign Fflow = subtraction ? ~adder_cout : adder_cout;
 end
 
+wire [31:0] mult_out_hi;
+wire [31:0] mult_out_lo;
+multiplier mult(A, B, mult_out_hi, mult_out_lo);
+
 assign O =
   op == 3'b000 ? adder_out :
   op == 3'b001 ? adder_out :
+  op == 3'b010 ? mult_out_hi :
+  op == 3'b011 ? mult_out_lo :
   op == 3'b100 ? A & B :
   op == 3'b101 ? A | B :
   op == 3'b110 ? A ^ B :

verilog-src/alu/multiplier.v

@@ -0,0 +1,12 @@
+module multiplier(
+  input [31:0] A,
+  input [31:0] B,
+  output [31:0] O_hi,
+  output [31:0] O_lo
+);
+
+wire [63:0] O = A * B;
+assign O_lo = O[31:0];
+assign O_hi = O[63:32];
+
+endmodule

verilog-src/topmost.v

@@ -0,0 +1,17 @@
+// Dummy module for connecting ALU and similar things, without having to break all inputs and outputs into separate pads
+module topmost(input clk, input [2:0] op, output xor_reduce);
+
+reg [31:0] A;
+reg [31:0] B;
+wire [31:0] O;
+
+alu alu(.A(A), .B(B), .op(op), .O(O), .Fflow(), .Fzero());
+
+always @(posedge clk) begin
+  A <= A + 1;
+  B <= B + 3;
+end
+
+assign xor_reduce = ^ O;
+
+endmodule