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Make verilator split carry array

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xenia 2024-01-17 14:38:27 +01:00
parent 4edeff9fe3
commit cdf37168cf
2 changed files with 3 additions and 3 deletions
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2
src/alu/alu.v
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@ -22,7 +22,7 @@ module alu(
wire [31:0] adder_out; wire [31:0] adder_out;
begin begin : addsub
wire addition = op == 3'b000; wire addition = op == 3'b000;
wire subtraction = op == 3'b001; wire subtraction = op == 3'b001;
wire [31:0] adder_B = subtraction ? ~B : B; wire [31:0] adder_B = subtraction ? ~B : B;

4
src/alu/carry_select_block.v
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@ -11,8 +11,8 @@ module carry_select_block#(
// Case for Cin = 0 // Case for Cin = 0
wire [N-1:0] O_C0; wire [N-1:0] O_C0;
wire [N-1:0] O_C1; wire [N-1:0] O_C1;
wire [N:1] carry0; wire carry0[N:1] /*verilator split_var*/;
wire [N:1] carry1; wire carry1[N:1] /*verilator split_var*/;
fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]); fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]); fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);