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updated docs

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This commit is contained in:
eiowlta 2023-07-23 14:44:51 +03:00
parent 3180f39514
commit fac2865075
3 changed files with 8 additions and 4 deletions
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1
docs/cpu.md
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@ -162,6 +162,7 @@ data.16 0x8700 data.8 20 data.8 1
| 2 | word (32 bits) | 2 | word (32 bits)
| 3 | reserved | 3 | reserved
For SLA, SRA, SRL, ROR, ROL, BCL, BSE, BTS, src immediates are fixed to 8 bits
## Interrupts and Exceptions ## Interrupts and Exceptions

7
docs/encoding.md
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@ -1,7 +1,7 @@
# Encoding # Encoding
``` ```
size instr . cond dest src <src> <dest> size instr off cond dest src <src> <srcoff> <dest> <dstoff>
xx xxxxxx 0 xxx xx xx <8,16,32 bits> <8,16,32 bits> xx xxxxxx x xxx xx xx <8,16,32 bits> <8 bits> <8,16,32 bits> <8 bits>
``` ```
@ -49,3 +49,6 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
| 0b01 | register (pointer) | | 0b01 | register (pointer) |
| 0b10 | immediate | | 0b10 | immediate |
| 0b11 | immediate (pointer) | | 0b11 | immediate (pointer) |
# Register Pointer Offset
The off field indicates that each operand of type 0b01 (register pointer) has an 8 bit immediate. This immediate is added to the value of the register before derefencing.

4
docs/instructions.md
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@ -8,8 +8,8 @@ description of the fox32 CPU and instruction encoding details, see [cpu.md](./cp
### ADD: add ### ADD: add
### SUB: subtract ### SUB: subtract
### INC: increment (add 1) ### INC: increment (add 1/2/4/8)
### DEC: decrement (subtract 1) ### DEC: decrement (subtract 1/2/4/8)
### CMP: compare ### CMP: compare
### AND: bitwise AND ### AND: bitwise AND
### OR: bitwise OR ### OR: bitwise OR