40 lines
780 B
Verilog
40 lines
780 B
Verilog
module carry_select_block#(
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parameter N = 4
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) (
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input [N-1:0] A,
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input [N-1:0] B,
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input Cin,
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output [N-1:0] O,
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output Cout
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);
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// Case for Cin = 0
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wire [N-1:0] O_C0;
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wire Cout_C0;
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begin
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wire [N-1:1] carry;
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fa fa0(A[0], B[0], 0, O_C0[0], carry[1]);
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genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
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fa fai(A[i], B[i], carry[i], O_C0[i], carry[i+1]);
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end
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assign Cout_C0 = carry[N-1];
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end
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// Case for Cin = 1
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wire [N-1:0] O_C1;
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wire Cout_C1;
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begin
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wire [N-1:1] carry;
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fa fa0(A[0], B[0], 1, O_C1[0], carry[1]);
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genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
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fa fai(A[i], B[i], carry[i], O_C1[i], carry[i+1]);
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end
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assign Cout_C1 = carry[N-1];
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end
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assign O = Cin == 0 ? O_C0 : O_C1;
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assign Cout = Cin == 0 ? Cout_C0 : Cout_C1;
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endmodule
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