flake.nix

@@ -15,9 +15,9 @@
           vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -Wno-PINCONNECTEMPTY -CFLAGS "-Wpedantic -std=c++20"'';
 
           verilate-src = cmd: ''
-            cp -r ${./src} ./src
+            cp -r ${./verilog-src} ./verilog-src
             cp -r ${./simulation} ./simulation
-            find ./src/ -name '*.v' -exec ${verilator}/bin/verilator ${vflags} ${cmd} {} +
+            find ./verilog-src/ -name '*.v' -exec ${verilator}/bin/verilator ${vflags} ${cmd} {} +
           '';
 
           lint = pkgs.runCommand "lint" {} ''
@@ -27,14 +27,14 @@
           '';
 
           alu-sim = pkgs.runCommandCC "alu-sim" {} ''
-            ${verilate-src "--cc --build --exe ./simulation/tester.cpp ./simulation/test_alu.cpp -top alu"}
+            ${verilate-src "--cc --build --exe ./simulation/tester.cpp ./simulation/test_alu.cpp"}
             mv obj_dir "$out"
             mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim"
           '';
 
           alu-synth = pkgs.runCommandCC "alu-synth" {} ''
             mkdir -p "$out"
-            find ${./src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
+            find ${./verilog-src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
           '';
 
           alu-synth-view = pkgs.writeScriptBin "alu-synth-view" ''

simulation/test_alu.cpp

@@ -1,9 +1,7 @@
 #include "Valu.h"
 #include "verilated.h"
 #include "tester.hpp"
-
 #include <stdint.h>
-#include <random>
 
 struct alu_testcase {
     std::string name;
@@ -18,18 +16,6 @@ struct alu_testcase {
     std::optional<unsigned int> max_cycles;
 };
 
-std::string fmt_hex(uint32_t n) {
-    char hex[100];
-    if (n < 0x100)
-        snprintf(hex, sizeof hex, "0x%02x", n);
-    else if (n < 0x10000)
-        snprintf(hex, sizeof hex, "0x%04x", n);
-    else
-        snprintf(hex, sizeof hex, "0x%08x", n);
-
-    return hex;
-}
-
 void test_op(Valu *valu, Tester *tester, alu_testcase test) {
     Tester subtester(tester, test.name);
 
@@ -40,9 +26,13 @@ void test_op(Valu *valu, Tester *tester, alu_testcase test) {
 
     valu->eval();
 
-    std::string o_name("O == ");
+    char o_name[100];
-    o_name.append(fmt_hex(test.O));
+    if (test.O < 0x100)
-
+        snprintf(o_name, sizeof o_name, "O == 0x%02x", test.O);
+    if (test.O < 0x10000)
+        snprintf(o_name, sizeof o_name, "O == 0x%04x", test.O);
+    else
+        snprintf(o_name, sizeof o_name, "O == 0x%08x", test.O);
     subtester.assert_eq(o_name, valu->O, test.O);
 
     if (test.overflow.has_value()) {
@@ -175,92 +165,4 @@ int main(int argc, char **argv) {
             .O = 0x0, .zero = true,
         });
     }
-
-    {
-        Tester auto_t(&alu_t, "auto", true);
-
-        std::default_random_engine eng;
-        std::uniform_int_distribution<uint32_t> op_gen(0, 5);
-        std::uniform_int_distribution<uint32_t> gen(0, 0xffffffff);
-
-        for (int i = 0; i < 100; i++) {
-            uint32_t A = gen(eng);
-            uint32_t B = gen(eng);
-            std::string name;
-
-            switch (op_gen(eng)) {
-            case 0: // Add
-                name.append(fmt_hex(A));
-                name.append("+");
-                name.append(fmt_hex(B));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b000,
-                    .O = A + B, .overflow = (A + B < A), .zero = (A + B == 0),
-                });
-
-                break;
-            case 1: // Subtract
-                name.append(fmt_hex(A));
-                name.append("-");
-                name.append(fmt_hex(B));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b001,
-                    .O = A - B, .overflow = (B > A), .zero = (A == B),
-                });
-
-                break;
-            case 2: // Bitwise AND
-                name.append(fmt_hex(A));
-                name.append("&");
-                name.append(fmt_hex(B));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b100,
-                    .O = A & B, .overflow = 0, .zero = ((A & B) == 0),
-                });
-
-                break;
-            case 3: // Bitwise OR
-                name.append(fmt_hex(A));
-                name.append("|");
-                name.append(fmt_hex(B));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b101,
-                    .O = A | B, .overflow = 0, .zero = ((A | B) == 0),
-                });
-
-                break;
-            case 4: // Bitwise XOR
-                name.append(fmt_hex(A));
-                name.append("^");
-                name.append(fmt_hex(B));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b110,
-                    .O = A ^ B, .overflow = 0, .zero = ((A ^ B) == 0),
-                });
-
-                break;
-            case 5: // Bitwise NOT
-                name.append("~");
-                name.append(fmt_hex(A));
-
-                test_op(valu, &auto_t, {
-                    .name = name,
-                    .A = A, .B = B, .op = 0b111,
-                    .O = ~A, .overflow = 0, .zero = (A == 0xffffffff),
-                });
-
-                break;
-            }
-        }
-    }
 }

verilog-src/alu.v

@@ -23,16 +23,12 @@ module alu(
 wire [31:0] adder_out;
 
 begin
-  wire addition = op == 3'b000;
   wire subtraction = op == 3'b001;
   wire [31:0] adder_B = subtraction ? ~B : B;
   wire adder_cout;
 
   carry_select_adder a(A, adder_B, subtraction, adder_out, adder_cout);
-  assign Fflow =
+  assign Fflow = subtraction ? ~adder_cout : adder_cout;
-    addition ? adder_cout :
-    subtraction ? ~adder_cout :
-    0;
 end
 
 wire [31:0] mult_out_hi;