fox32-hw/verilog-src/alu.v

/*
  A and B are inputs, O is out
  OP is the operation to perform:
    000 = add
    001 = sub
    010 = mul
    (011)
    100 = and
    101 = or
    110 = xor
    111 = not A
*/
module alu(
  input [31:0] A,
  input [31:0] B,
  input [2:0] op,
  output [31:0] O,
  output Fflow,
  output Fzero
);

wire subtraction = op == 3'b001;
wire [31:0] adder_B = subtraction ? ~B : B;
wire adder_cout;

carry_select_adder a(A, adder_B, subtraction, O, adder_cout);

assign Fflow = subtraction ? ~adder_cout : adder_cout;
assign Fzero = ~ (| O);

endmodule