fox32-hw/verilog-src/alu.v

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2024-01-12 13:44:33 +01:00
/*
A and B are inputs, O is out
OP is the operation to perform:
000 = add
001 = sub
010 = mul
(011)
100 = and
101 = or
110 = xor
111 = not A
*/
module alu(
input [31:0] A,
input [31:0] B,
input [2:0] op,
output [31:0] O,
output Cout,
output Fzero
);
wire subtraction = op == 3'b001;
wire [31:0] adder_B = subtraction ? ~B : B;
carry_select_adder a(A, adder_B, subtraction, O, Cout);
assign Fzero = & O;
endmodule