fox32-hw/verilog-src/alu/multiplier.v

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2024-01-17 12:24:33 +01:00
module multiplier(
input [31:0] A,
input [31:0] B,
output [31:0] O_hi,
output [31:0] O_lo
);
wire [63:0] O = A * B;
assign O_lo = O[31:0];
assign O_hi = O[63:32];
endmodule