fox32-hw/verilog-src/alu/carry_select_adder.v

// 5 blocks of size 6, final block of size 2
module carry_select_adder(
  input [31:0] A,
  input [31:0] B,
  input Cin,
  output [31:0] O,
  output Cout
);

// TODO: First block should not be carry_select, a normal RCA is better
// i think?
wire Cout_5;
carry_select_block#(6) B0 (A[5:0], B[5:0], Cin, O[5:0], Cout_5);

wire Cout_11;
carry_select_block#(6) B1 (A[11:6], B[11:6], Cout_5, O[11:6], Cout_11);

wire Cout_17;
carry_select_block#(6) B2 (A[17:12], B[17:12], Cout_11, O[17:12], Cout_17);

wire Cout_23;
carry_select_block#(6) B3 (A[23:18], B[23:18], Cout_17, O[23:18], Cout_23);

wire Cout_29;
carry_select_block#(6) B4 (A[29:24], B[29:24], Cout_23, O[29:24], Cout_29);

carry_select_block#(2) B5 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);

endmodule