fox32+fox32asm: Remove pow instruction
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@ -17,7 +17,7 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
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| 0x | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
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| :-: | ---- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | -------------- | ---- | ----- | -------------- | --- | --- | --- | --- | --- |
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| 0- | NOP | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32] | SRA[.8,16,32] | BSE[.8,16,32] | CMP[.8,16,32] | JMP | RJMP | PUSH[.8,16,32] | IN | ISE | | | |
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| 1- | HALT | INC[.8,16,32] | POW[.8,16,32] | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | |
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| 1- | HALT | INC[.8,16,32] | | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | |
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| 2- | BRK | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32] | ROR[.8,16,32] | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET | | | | | |
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| 3- | | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | | | | | | RTA | RETI | | | | | |
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92
src/cpu.rs
92
src/cpu.rs
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@ -794,96 +794,6 @@ impl Cpu {
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}
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self.instruction_pointer + instruction_pointer_offset
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}
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Instruction::Pow(size, condition, destination, source) => {
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let (source_value, mut instruction_pointer_offset) = self.read_source(source);
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let should_run = self.check_condition(condition);
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match destination {
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Operand::Register => {
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let register = self.bus.memory.read_8(self.instruction_pointer + instruction_pointer_offset);
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match size {
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Size::Byte => {
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if should_run {
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let result = (self.read_register(register) as u8).pow(source_value);
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self.write_register(register, (self.read_register(register) & 0xFFFFFF00) | (result as u32));
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self.flag.zero = result == 0;
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}
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}
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Size::Half => {
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if should_run {
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let result = (self.read_register(register) as u16).pow(source_value);
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self.write_register(register, (self.read_register(register) & 0xFFFF0000) | (result as u32));
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self.flag.zero = result == 0;
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}
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}
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Size::Word => {
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if should_run {
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let result = self.read_register(register).pow(source_value);
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self.write_register(register, result);
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self.flag.zero = result == 0;
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}
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}
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}
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instruction_pointer_offset += 1; // increment past 8 bit register number
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}
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Operand::RegisterPtr => {
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let register = self.bus.memory.read_8(self.instruction_pointer + instruction_pointer_offset);
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let pointer = self.read_register(register);
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match size {
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Size::Byte => {
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let result = self.bus.memory.read_8(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_8(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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Size::Half => {
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let result = self.bus.memory.read_16(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_16(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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Size::Word => {
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let result = self.bus.memory.read_32(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_32(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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}
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instruction_pointer_offset += 1; // increment past 8 bit register number
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}
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Operand::ImmediatePtr(_) => {
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let pointer = self.bus.memory.read_32(self.instruction_pointer + instruction_pointer_offset);
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match size {
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Size::Byte => {
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let result = self.bus.memory.read_8(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_8(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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Size::Half => {
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let result = self.bus.memory.read_16(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_16(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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Size::Word => {
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let result = self.bus.memory.read_32(pointer).pow(source_value);
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if should_run {
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self.bus.memory.write_32(pointer, result);
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self.flag.zero = result == 0;
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}
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}
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}
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instruction_pointer_offset += 4; // increment past 32 bit pointer
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}
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_ => panic!("Attempting to use an immediate value as a destination"),
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}
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self.instruction_pointer + instruction_pointer_offset
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}
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Instruction::Div(size, condition, destination, source) => {
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let (source_value, mut instruction_pointer_offset) = self.read_source(source);
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let should_run = self.check_condition(condition);
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@ -2707,7 +2617,6 @@ enum Instruction {
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Dec(Size, Condition, Operand),
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Mul(Size, Condition, Operand, Operand),
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Pow(Size, Condition, Operand, Operand),
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Div(Size, Condition, Operand, Operand),
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Rem(Size, Condition, Operand, Operand),
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@ -2802,7 +2711,6 @@ impl Instruction {
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0x31 => Some(Instruction::Dec(size, condition, source)),
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0x02 => Some(Instruction::Mul(size, condition, destination, source)),
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0x12 => Some(Instruction::Pow(size, condition, destination, source)),
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0x22 => Some(Instruction::Div(size, condition, destination, source)),
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0x32 => Some(Instruction::Rem(size, condition, destination, source)),
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