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fox32+fox32asm: Remove pow instruction

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Ry 2022-05-30 00:48:19 -07:00
parent 5deb4fd8f8
commit e8960c569f
2 changed files with 2 additions and 94 deletions
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4
encoding.md
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@ -17,7 +17,7 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
| 0x | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F | | 0x | -0 | -1 | -2 | -3 | -4 | -5 | -6 | -7 | -8 | -9 | -A | -B | -C | -D | -E | -F |
| :-: | ---- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | -------------- | ---- | ----- | -------------- | --- | --- | --- | --- | --- | | :-: | ---- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | -------------- | ---- | ----- | -------------- | --- | --- | --- | --- | --- |
| 0- | NOP | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32] | SRA[.8,16,32] | BSE[.8,16,32] | CMP[.8,16,32] | JMP | RJMP | PUSH[.8,16,32] | IN | ISE | | | | | 0- | NOP | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32] | SRA[.8,16,32] | BSE[.8,16,32] | CMP[.8,16,32] | JMP | RJMP | PUSH[.8,16,32] | IN | ISE | | | |
| 1- | HALT | INC[.8,16,32] | POW[.8,16,32] | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | | | 1- | HALT | INC[.8,16,32] | | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | |
| 2- | BRK | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32] | ROR[.8,16,32] | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET | | | | | | | 2- | BRK | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32] | ROR[.8,16,32] | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET | | | | | |
| 3- | | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | | | | | | RTA | RETI | | | | | | | 3- | | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | | | | | | RTA | RETI | | | | | |
@ -48,4 +48,4 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
| 0b00 | register | | 0b00 | register |
| 0b01 | register (pointer) | | 0b01 | register (pointer) |
| 0b10 | immediate | | 0b10 | immediate |
| 0b11 | immediate (pointer) | | 0b11 | immediate (pointer) |

92
src/cpu.rs
View File

@ -794,96 +794,6 @@ impl Cpu {
} }
self.instruction_pointer + instruction_pointer_offset self.instruction_pointer + instruction_pointer_offset
} }
Instruction::Pow(size, condition, destination, source) => {
let (source_value, mut instruction_pointer_offset) = self.read_source(source);
let should_run = self.check_condition(condition);
match destination {
Operand::Register => {
let register = self.bus.memory.read_8(self.instruction_pointer + instruction_pointer_offset);
match size {
Size::Byte => {
if should_run {
let result = (self.read_register(register) as u8).pow(source_value);
self.write_register(register, (self.read_register(register) & 0xFFFFFF00) | (result as u32));
self.flag.zero = result == 0;
}
}
Size::Half => {
if should_run {
let result = (self.read_register(register) as u16).pow(source_value);
self.write_register(register, (self.read_register(register) & 0xFFFF0000) | (result as u32));
self.flag.zero = result == 0;
}
}
Size::Word => {
if should_run {
let result = self.read_register(register).pow(source_value);
self.write_register(register, result);
self.flag.zero = result == 0;
}
}
}
instruction_pointer_offset += 1; // increment past 8 bit register number
}
Operand::RegisterPtr => {
let register = self.bus.memory.read_8(self.instruction_pointer + instruction_pointer_offset);
let pointer = self.read_register(register);
match size {
Size::Byte => {
let result = self.bus.memory.read_8(pointer).pow(source_value);
if should_run {
self.bus.memory.write_8(pointer, result);
self.flag.zero = result == 0;
}
}
Size::Half => {
let result = self.bus.memory.read_16(pointer).pow(source_value);
if should_run {
self.bus.memory.write_16(pointer, result);
self.flag.zero = result == 0;
}
}
Size::Word => {
let result = self.bus.memory.read_32(pointer).pow(source_value);
if should_run {
self.bus.memory.write_32(pointer, result);
self.flag.zero = result == 0;
}
}
}
instruction_pointer_offset += 1; // increment past 8 bit register number
}
Operand::ImmediatePtr(_) => {
let pointer = self.bus.memory.read_32(self.instruction_pointer + instruction_pointer_offset);
match size {
Size::Byte => {
let result = self.bus.memory.read_8(pointer).pow(source_value);
if should_run {
self.bus.memory.write_8(pointer, result);
self.flag.zero = result == 0;
}
}
Size::Half => {
let result = self.bus.memory.read_16(pointer).pow(source_value);
if should_run {
self.bus.memory.write_16(pointer, result);
self.flag.zero = result == 0;
}
}
Size::Word => {
let result = self.bus.memory.read_32(pointer).pow(source_value);
if should_run {
self.bus.memory.write_32(pointer, result);
self.flag.zero = result == 0;
}
}
}
instruction_pointer_offset += 4; // increment past 32 bit pointer
}
_ => panic!("Attempting to use an immediate value as a destination"),
}
self.instruction_pointer + instruction_pointer_offset
}
Instruction::Div(size, condition, destination, source) => { Instruction::Div(size, condition, destination, source) => {
let (source_value, mut instruction_pointer_offset) = self.read_source(source); let (source_value, mut instruction_pointer_offset) = self.read_source(source);
let should_run = self.check_condition(condition); let should_run = self.check_condition(condition);
@ -2707,7 +2617,6 @@ enum Instruction {
Dec(Size, Condition, Operand), Dec(Size, Condition, Operand),
Mul(Size, Condition, Operand, Operand), Mul(Size, Condition, Operand, Operand),
Pow(Size, Condition, Operand, Operand),
Div(Size, Condition, Operand, Operand), Div(Size, Condition, Operand, Operand),
Rem(Size, Condition, Operand, Operand), Rem(Size, Condition, Operand, Operand),
@ -2802,7 +2711,6 @@ impl Instruction {
0x31 => Some(Instruction::Dec(size, condition, source)), 0x31 => Some(Instruction::Dec(size, condition, source)),
0x02 => Some(Instruction::Mul(size, condition, destination, source)), 0x02 => Some(Instruction::Mul(size, condition, destination, source)),
0x12 => Some(Instruction::Pow(size, condition, destination, source)),
0x22 => Some(Instruction::Div(size, condition, destination, source)), 0x22 => Some(Instruction::Div(size, condition, destination, source)),
0x32 => Some(Instruction::Rem(size, condition, destination, source)), 0x32 => Some(Instruction::Rem(size, condition, destination, source)),