Add int instruction, bump version to 0.2.0

This commit is contained in:
Ry 2022-08-09 01:41:13 -07:00
parent ad6f402179
commit 4b506f3e65
3 changed files with 15 additions and 4 deletions

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@ -1,12 +1,10 @@
[package] [package]
name = "fox32" name = "fox32"
version = "0.1.0" version = "0.2.0"
authors = ["ry"] authors = ["ry"]
edition = "2021" edition = "2021"
build = "build.rs" build = "build.rs"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies] [dependencies]
image = "0.24" image = "0.24"
log = "0.4" log = "0.4"

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@ -18,7 +18,7 @@ If the instruction doesn't allow variable sizes or a size was not specified, set
| :-: | ---- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | -------------- | ---- | ----- | -------------- | --- | --- | --- | --- | --- | | :-: | ---- | ------------- | ------------- | ------------- | ------------- | ------------- | ------------- | -------------- | ---- | ----- | -------------- | --- | --- | --- | --- | --- |
| 0- | NOP | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32] | SRA[.8,16,32] | BSE[.8,16,32] | CMP[.8,16,32] | JMP | RJMP | PUSH[.8,16,32] | IN | ISE | | | | | 0- | NOP | ADD[.8,16,32] | MUL[.8,16,32] | AND[.8,16,32] | SLA[.8,16,32] | SRA[.8,16,32] | BSE[.8,16,32] | CMP[.8,16,32] | JMP | RJMP | PUSH[.8,16,32] | IN | ISE | | | |
| 1- | HALT | INC[.8,16,32] | | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | | | 1- | HALT | INC[.8,16,32] | | OR[.8,16,32] | | SRL[.8,16,32] | BCL[.8,16,32] | MOV[.8,16,32] | CALL | RCALL | POP[.8,16,32] | OUT | ICL | | | |
| 2- | BRK | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32] | ROR[.8,16,32] | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET | | | | | | | 2- | BRK | SUB[.8,16,32] | DIV[.8,16,32] | XOR[.8,16,32] | ROL[.8,16,32] | ROR[.8,16,32] | BTS[.8,16,32] | MOVZ[.8,16,32] | LOOP | RLOOP | RET | | INT | | | |
| 3- | | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | | | | | | RTA | RETI | | | | | | | 3- | | DEC[.8,16,32] | REM[.8,16,32] | NOT[.8,16,32] | | | | | | RTA | RETI | | | | | |
# Condition table # Condition table

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@ -2571,6 +2571,17 @@ impl Cpu {
} }
self.instruction_pointer + instruction_pointer_offset self.instruction_pointer + instruction_pointer_offset
} }
Instruction::Int(condition, source) => {
let (source_value, instruction_pointer_offset) = self.read_source(source);
let should_run = self.check_condition(condition);
if should_run {
self.instruction_pointer += instruction_pointer_offset;
self.handle_interrupt(source_value as u16);
self.instruction_pointer
} else {
self.instruction_pointer + instruction_pointer_offset
}
}
} }
} }
} }
@ -2660,6 +2671,7 @@ enum Instruction {
Ise(Condition), Ise(Condition),
Icl(Condition), Icl(Condition),
Int(Condition, Operand),
} }
impl Instruction { impl Instruction {
@ -2754,6 +2766,7 @@ impl Instruction {
0x0C => Some(Instruction::Ise(condition)), 0x0C => Some(Instruction::Ise(condition)),
0x1C => Some(Instruction::Icl(condition)), 0x1C => Some(Instruction::Icl(condition)),
0x2C => Some(Instruction::Int(condition, source)),
_ => None, _ => None,
} }