13 lines
183 B
Verilog
13 lines
183 B
Verilog
module multiplier(
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input [31:0] A,
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input [31:0] B,
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output [31:0] O_hi,
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output [31:0] O_lo
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);
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wire [63:0] O = A * B;
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assign O_lo = O[31:0];
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assign O_hi = O[63:32];
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endmodule
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