30 lines
765 B
Verilog
30 lines
765 B
Verilog
// 5 blocks of size 6, final block of size 2
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module carry_select_adder(
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input [31:0] A,
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input [31:0] B,
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input Cin,
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output [31:0] O,
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output Cout
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);
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// TODO: First block should not be carry_select, a normal RCA is better
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// i think?
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wire Cout_5;
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carry_select_block#(6) B0 (A[5:0], B[5:0], Cin, O[5:0], Cout_5);
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wire Cout_11;
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carry_select_block#(6) B1 (A[11:6], B[11:6], Cout_5, O[11:6], Cout_11);
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wire Cout_17;
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carry_select_block#(6) B2 (A[17:12], B[17:12], Cout_11, O[17:12], Cout_17);
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wire Cout_23;
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carry_select_block#(6) B3 (A[23:18], B[23:18], Cout_17, O[23:18], Cout_23);
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wire Cout_29;
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carry_select_block#(6) B4 (A[29:24], B[29:24], Cout_23, O[29:24], Cout_29);
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carry_select_block#(2) B6 (A[31:30], B[31:30], Cout_29, O[31:30], Cout);
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endmodule
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