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fpga-files
|
Start work on ALU
|
2024-01-12 13:44:33 +01:00 |
|
simulation
|
Remove old simulation
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2024-01-12 18:36:11 +01:00 |
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verilog-src
|
Start work on ALU
|
2024-01-12 13:44:33 +01:00 |
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.envrc
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
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.gitignore
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initial commit
|
2024-01-10 22:10:01 +01:00 |
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flake.lock
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initial commit
|
2024-01-10 22:10:01 +01:00 |
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flake.nix
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Rename project
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2024-01-12 13:45:05 +01:00 |
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verilator.nix
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
