45 lines
773 B
Verilog
45 lines
773 B
Verilog
/*
|
|
A and B are inputs, O is out
|
|
OP is the operation to perform:
|
|
000 = add
|
|
001 = sub
|
|
010 = mul
|
|
(011)
|
|
100 = and
|
|
101 = or
|
|
110 = xor
|
|
111 = not A
|
|
*/
|
|
module alu(
|
|
input [31:0] A,
|
|
input [31:0] B,
|
|
input [2:0] op,
|
|
output [31:0] O,
|
|
output Fflow,
|
|
output Fzero
|
|
);
|
|
|
|
wire [31:0] adder_out;
|
|
|
|
begin
|
|
wire subtraction = op == 3'b001;
|
|
wire [31:0] adder_B = subtraction ? ~B : B;
|
|
wire adder_cout;
|
|
|
|
carry_select_adder a(A, adder_B, subtraction, adder_out, adder_cout);
|
|
assign Fflow = subtraction ? ~adder_cout : adder_cout;
|
|
end
|
|
|
|
assign O =
|
|
op == 3'b000 ? adder_out :
|
|
op == 3'b001 ? adder_out :
|
|
op == 3'b100 ? A & B :
|
|
op == 3'b101 ? A | B :
|
|
op == 3'b110 ? A ^ B :
|
|
op == 3'b111 ? ~A :
|
|
'0;
|
|
|
|
assign Fzero = ~ (| O);
|
|
|
|
endmodule
|