32 lines
548 B
Verilog
32 lines
548 B
Verilog
/*
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A and B are inputs, O is out
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OP is the operation to perform:
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000 = add
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001 = sub
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010 = mul
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(011)
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100 = and
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101 = or
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110 = xor
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111 = not A
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*/
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module alu(
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input [31:0] A,
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input [31:0] B,
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input [2:0] op,
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output [31:0] O,
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output Fflow,
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output Fzero
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);
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wire subtraction = op == 3'b001;
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wire [31:0] adder_B = subtraction ? ~B : B;
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wire adder_cout;
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carry_select_adder a(A, adder_B, subtraction, O, adder_cout);
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assign Fflow = subtraction ? ~adder_cout : adder_cout;
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assign Fzero = ~ (| O);
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endmodule
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