|
fpga-files
|
Synthesizing
|
2024-01-17 12:25:46 +01:00 |
|
simulation
|
Make ALU synchronous, generate and view traces
|
2024-01-21 20:50:22 +01:00 |
|
src
|
Make ALU synchronous, generate and view traces
|
2024-01-21 20:50:22 +01:00 |
|
.envrc
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
|
.gitignore
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
|
flake.lock
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
|
flake.nix
|
Don't warn on BLKSEQ
|
2024-01-21 20:50:47 +01:00 |
|
verilator.nix
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
