8 lines
168 B
Verilog
8 lines
168 B
Verilog
// One bit full-adder
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module fa(input A, input B, input Cin, output O, output Cout);
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assign O = A ^ B ^ Cin;
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assign Cout = (A & B) | (B & Cin) | (Cin & A);
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endmodule
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