{ description = "fox32 on FPGA"; inputs = { flake-utils.url = "github:numtide/flake-utils"; }; outputs = { self, nixpkgs, flake-utils }: flake-utils.lib.eachDefaultSystem (sys: let pkgs = nixpkgs.legacyPackages.${sys}; verilator = import ./verilator.nix pkgs ; yosys = pkgs.yosys; vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -Wno-PINCONNECTEMPTY -CFLAGS "-Wpedantic -std=c++20"''; verilate-src = cmd: '' cp -r ${./src} ./src cp -r ${./simulation} ./simulation find ./src/ -name '*.v' -exec ${verilator}/bin/verilator ${vflags} ${cmd} {} + ''; lint = pkgs.runCommand "lint" {} '' ${verilate-src "--lint-only"} echo "compiler didn't get angry :3" : 3 > $out ''; alu-sim = pkgs.runCommandCC "alu-sim" {} '' ${verilate-src "--cc --build --exe ./simulation/tester.cpp ./simulation/test_alu.cpp -top alu"} mv obj_dir "$out" mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim" ''; alu-sim-trace = pkgs.runCommandCC "alu-sim-trace" {} '' ${verilate-src "--cc --build --exe --trace -CFLAGS -DTRACE=1 ./simulation/tester.cpp ./simulation/test_alu.cpp -top alu"} mv obj_dir "$out" mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim" $out/bin/alu-sim $out/trace.vcd echo "${pkgs.gtkwave}/bin/gtkwave $out/trace.vcd" > $out/bin/alu-sim-trace chmod u+x $out/bin/alu-sim-trace ''; alu-synth = pkgs.runCommandCC "alu-synth" {} '' mkdir -p "$out" find ${./src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} + ''; alu-synth-view = pkgs.writeScriptBin "alu-synth-view" '' ${pkgs.nextpnrWithGui}/bin/nextpnr-ice40 --up5k --package sg48 --pcf ${./fpga-files/rot.pcf} --json ${alu-synth}/synth.json --gui ''; deps = [ yosys pkgs.nextpnrWithGui pkgs.icestorm verilator pkgs.gtkwave ]; in rec { packages.verilator = verilator; packages.lint = lint; packages.alu-sim = alu-sim; packages.alu-sim-trace = alu-sim-trace; packages.alu-synth = alu-synth; packages.alu-synth-view = alu-synth-view; devShells.default = pkgs.mkShell { packages = deps; }; } ); }