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f475483803
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Rename nix targets
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2024-01-21 22:59:48 +01:00 |
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ba09e75c57
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Multiplication implementation
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2024-01-21 22:41:21 +01:00 |
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ac3e34b2ef
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Don't warn on BLKSEQ
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2024-01-21 22:41:21 +01:00 |
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14cf222a6c
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Make ALU synchronous, generate and view traces
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2024-01-21 22:41:18 +01:00 |
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fb65ccc713
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Move verilog-src to src, src/alu.v to src/alu/alu.v
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2024-01-17 13:37:02 +01:00 |
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69c367c344
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Synthesizing
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2024-01-17 12:25:46 +01:00 |
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d0dbbfee82
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Don't warn on PINCONNECTEMPTY
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2024-01-17 12:24:12 +01:00 |
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1f53f7e90f
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Pretty up the testing framework, split into files
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2024-01-12 22:32:45 +01:00 |
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49bad232bc
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Add -Wpedantic to CFLAGS
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2024-01-12 20:44:16 +01:00 |
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69dbe3b7c6
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Rename project
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2024-01-12 13:45:05 +01:00 |
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e9b8d44104
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Start work on ALU
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2024-01-12 13:44:33 +01:00 |
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8c126980a6
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initial commit
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2024-01-10 22:10:01 +01:00 |
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