|
|
3b10fd110e
|
Don't warn on BLKSEQ
|
2024-01-21 20:50:47 +01:00 |
|
|
|
1b316ead40
|
Make ALU synchronous, generate and view traces
|
2024-01-21 20:50:22 +01:00 |
|
|
|
fb65ccc713
|
Move verilog-src to src, src/alu.v to src/alu/alu.v
|
2024-01-17 13:37:02 +01:00 |
|
|
|
69c367c344
|
Synthesizing
|
2024-01-17 12:25:46 +01:00 |
|
|
|
d0dbbfee82
|
Don't warn on PINCONNECTEMPTY
|
2024-01-17 12:24:12 +01:00 |
|
|
|
1f53f7e90f
|
Pretty up the testing framework, split into files
|
2024-01-12 22:32:45 +01:00 |
|
|
|
49bad232bc
|
Add -Wpedantic to CFLAGS
|
2024-01-12 20:44:16 +01:00 |
|
|
|
69dbe3b7c6
|
Rename project
|
2024-01-12 13:45:05 +01:00 |
|
|
|
e9b8d44104
|
Start work on ALU
|
2024-01-12 13:44:33 +01:00 |
|
|
|
8c126980a6
|
initial commit
|
2024-01-10 22:10:01 +01:00 |
|
