Move verilog-src to src, src/alu.v to src/alu/alu.v

flake.nix

@@ -15,9 +15,9 @@
           vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -Wno-PINCONNECTEMPTY -CFLAGS "-Wpedantic -std=c++20"'';
 
           verilate-src = cmd: ''
-            cp -r ${./verilog-src} ./verilog-src
+            cp -r ${./src} ./src
             cp -r ${./simulation} ./simulation
-            find ./verilog-src/ -name '*.v' -exec ${verilator}/bin/verilator ${vflags} ${cmd} {} +
+            find ./src/ -name '*.v' -exec ${verilator}/bin/verilator ${vflags} ${cmd} {} +
           '';
 
           lint = pkgs.runCommand "lint" {} ''
@@ -27,14 +27,14 @@
           '';
 
           alu-sim = pkgs.runCommandCC "alu-sim" {} ''
-            ${verilate-src "--cc --build --exe ./simulation/tester.cpp ./simulation/test_alu.cpp"}
+            ${verilate-src "--cc --build --exe ./simulation/tester.cpp ./simulation/test_alu.cpp -top alu"}
             mv obj_dir "$out"
             mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim"
           '';
 
           alu-synth = pkgs.runCommandCC "alu-synth" {} ''
             mkdir -p "$out"
-            find ${./verilog-src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
+            find ${./src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
           '';
 
           alu-synth-view = pkgs.writeScriptBin "alu-synth-view" ''