diff --git a/simulation/test_alu.cpp b/simulation/test_alu.cpp
index c0601e4..7510969 100644
--- a/simulation/test_alu.cpp
+++ b/simulation/test_alu.cpp
@@ -32,6 +32,17 @@ int main(int argc, char **argv) {
             add_case.assert_eq("no Fzero", valu->Fzero, 0x0);
         }
 
+        {
+            Tester add_case(&add_t, "0x5555+0x5555");
+            valu->op = 0b000;
+            valu->A = 0x5555;
+            valu->B = 0x5555;
+            valu->eval();
+            add_case.assert_eq("O == 0xaaaa", valu->O, 0xaaaa);
+            add_case.assert_eq("no overflow", valu->Fflow, 0x0);
+            add_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        }
+
         {
             Tester add_case(&add_t, "0xffffffff+0x1");
             valu->op = 0b000;
diff --git a/verilog-src/alu/carry_select_block.v b/verilog-src/alu/carry_select_block.v
index ffd7d8b..ca2cd0d 100644
--- a/verilog-src/alu/carry_select_block.v
+++ b/verilog-src/alu/carry_select_block.v
@@ -10,30 +10,18 @@ module carry_select_block#(
 
 // Case for Cin = 0
 wire [N-1:0] O_C0;
-wire Cout_C0;
-
-begin
-  wire [N-1:1] carry;
-  fa fa0(A[0], B[0], 0, O_C0[0], carry[1]);
-  genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
-    fa fai(A[i], B[i], carry[i], O_C0[i], carry[i+1]);
-  end
-  assign Cout_C0 = carry[N-1];
-end
-
-// Case for Cin = 1
 wire [N-1:0] O_C1;
-wire Cout_C1;
-begin
-  wire [N-1:1] carry;
-  fa fa0(A[0], B[0], 1, O_C1[0], carry[1]);
-  genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
-    fa fai(A[i], B[i], carry[i], O_C1[i], carry[i+1]);
-  end
-  assign Cout_C1 = carry[N-1];
+wire [N:1] carry0;
+wire [N:1] carry1;
+
+fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
+fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);
+genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
+  fa fa0i(A[i], B[i], carry0[i], O_C0[i], carry0[i+1]);
+  fa fa1i(A[i], B[i], carry1[i], O_C1[i], carry1[i+1]);
 end
 
 assign O = Cin == 0 ? O_C0 : O_C1;
-assign Cout = Cin == 0 ? Cout_C0 : Cout_C1;
+assign Cout = Cin == 0 ? carry0[N] : carry1[N];
 
 endmodule