From 87052a2f4ed23d204268ce4bfbeed06d1143d540 Mon Sep 17 00:00:00 2001
From: xenia <xenia.agda@gmail.com>
Date: Sat, 13 Jan 2024 00:16:28 +0100
Subject: [PATCH] Implement bitwise operations

---
 simulation/test_alu.cpp | 41 +++++++++++++++++++++++++++++++++++++++++
 verilog-src/alu.v       | 23 ++++++++++++++++++-----
 2 files changed, 59 insertions(+), 5 deletions(-)

diff --git a/simulation/test_alu.cpp b/simulation/test_alu.cpp
index 7510969..168ffa6 100644
--- a/simulation/test_alu.cpp
+++ b/simulation/test_alu.cpp
@@ -103,5 +103,46 @@ int main(int argc, char **argv) {
         }
     }
 
+    {
+        Tester bitwise_t(&alu_t, "bitwise");
+        // 0x3 = 0b0011, 0x5 = 0b0101
+        {
+            Tester and_case(&bitwise_t, "0x3&0x5");
+            valu->op = 0b100;
+            valu->A = 0x3;
+            valu->B = 0x5;
+            valu->eval();
+            and_case.assert_eq("O == 0x1", valu->O, 0x1);
+            and_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        }
 
+        {
+            Tester or_case(&bitwise_t, "0x3|0x5");
+            valu->op = 0b101;
+            valu->A = 0x3;
+            valu->B = 0x5;
+            valu->eval();
+            or_case.assert_eq("O == 0x7", valu->O, 0x7);
+            or_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        }
+
+        {
+            Tester xor_case(&bitwise_t, "0x3^0x5");
+            valu->op = 0b110;
+            valu->A = 0x3;
+            valu->B = 0x5;
+            valu->eval();
+            xor_case.assert_eq("O == 0x6", valu->O, 0x6);
+            xor_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        }
+
+        {
+            Tester xor_case(&bitwise_t, "~0xa5a5a5a5");
+            valu->op = 0b111;
+            valu->A = 0xa5a5a5a5;
+            valu->eval();
+            xor_case.assert_eq("O == 0x5a5a5a5a", valu->O, 0x5a5a5a5a);
+            xor_case.assert_eq("no Fzero", valu->Fzero, 0x0);
+        }
+    }
 }
diff --git a/verilog-src/alu.v b/verilog-src/alu.v
index 2a1465c..e5b055b 100644
--- a/verilog-src/alu.v
+++ b/verilog-src/alu.v
@@ -19,13 +19,26 @@ module alu(
   output Fzero
 );
 
-wire subtraction = op == 3'b001;
-wire [31:0] adder_B = subtraction ? ~B : B;
-wire adder_cout;
+wire [31:0] adder_out;
 
-carry_select_adder a(A, adder_B, subtraction, O, adder_cout);
+begin
+  wire subtraction = op == 3'b001;
+  wire [31:0] adder_B = subtraction ? ~B : B;
+  wire adder_cout;
+
+  carry_select_adder a(A, adder_B, subtraction, adder_out, adder_cout);
+  assign Fflow = subtraction ? ~adder_cout : adder_cout;
+end
+
+assign O =
+  op == 3'b000 ? adder_out :
+  op == 3'b001 ? adder_out :
+  op == 3'b100 ? A & B :
+  op == 3'b101 ? A | B :
+  op == 3'b110 ? A ^ B :
+  op == 3'b111 ? ~A :
+  '0;
 
-assign Fflow = subtraction ? ~adder_cout : adder_cout;
 assign Fzero = ~ (| O);
 
 endmodule