diff --git a/flake.nix b/flake.nix
index dcd3346..0561e2b 100644
--- a/flake.nix
+++ b/flake.nix
@@ -10,6 +10,7 @@
       let pkgs = nixpkgs.legacyPackages.${sys};
 
           verilator = import ./verilator.nix pkgs ;
+          yosys = pkgs.yosys;
 
           vflags = ''-Wpedantic -Wwarn-lint -Wwarn-style -Wno-PINCONNECTEMPTY -CFLAGS "-Wpedantic -std=c++20"'';
 
@@ -31,8 +32,17 @@
             mkdir "$out/bin" && cp "$out/Valu" "$out/bin/alu-sim"
           '';
 
-          deps = with pkgs; [
-            yosys nextpnrWithGui icestorm verilator
+          alu-synth = pkgs.runCommandCC "alu-synth" {} ''
+            mkdir -p "$out"
+            find ${./verilog-src} -name '*.v' -exec ${yosys}/bin/yosys -Q -p "synth_ice40 -top topmost -json $out/synth.json -dsp" {} +
+          '';
+
+          alu-synth-view = pkgs.writeScriptBin "alu-synth-view" ''
+            ${pkgs.nextpnrWithGui}/bin/nextpnr-ice40 --up5k --package sg48 --pcf ${./fpga-files/rot.pcf} --json ${alu-synth}/synth.json --gui
+          '';
+
+          deps = [
+            yosys pkgs.nextpnrWithGui pkgs.icestorm verilator
           ];
       in rec {
         packages.verilator = verilator;
@@ -40,6 +50,9 @@
         packages.lint = lint;
 
         packages.alu-sim = alu-sim;
+        packages.alu-synth = alu-synth;
+        packages.alu-synth-view = alu-synth-view;
+
         devShells.default = pkgs.mkShell {
           packages = deps;
         };
diff --git a/fpga-files/rot.pcf b/fpga-files/rot.pcf
index 1ce2c7c..3424530 100644
--- a/fpga-files/rot.pcf
+++ b/fpga-files/rot.pcf
@@ -1,5 +1,5 @@
-set_io D0 23
-set_io D1 27
-set_io D2 21
-set_io D3 25
-set_io clk 35
+set_io clk 39
+set_io op[0] 40
+set_io op[1] 41
+set_io op[2] 42
+set_io xor_reduce 10
diff --git a/verilog-src/topmost.v b/verilog-src/topmost.v
new file mode 100644
index 0000000..107a902
--- /dev/null
+++ b/verilog-src/topmost.v
@@ -0,0 +1,17 @@
+// Dummy module for connecting ALU and similar things, without having to break all inputs and outputs into separate pads
+module topmost(input clk, input [2:0] op, output xor_reduce);
+
+reg [31:0] A;
+reg [31:0] B;
+wire [31:0] O;
+
+alu alu(.A(A), .B(B), .op(op), .O(O), .Fflow(), .Fzero());
+
+always @(posedge clk) begin
+  A <= A + 1;
+  B <= B + 3;
+end
+
+assign xor_reduce = ^ O;
+
+endmodule