diff --git a/verilog-src/alu.v b/verilog-src/alu.v
index e5b055b..3b6b242 100644
--- a/verilog-src/alu.v
+++ b/verilog-src/alu.v
@@ -3,7 +3,8 @@
   OP is the operation to perform:
     000 = add
     001 = sub
-    010 = mul
+    010 = mul_lo
+    011 = mul_hi
     (011)
     100 = and
     101 = or
@@ -30,9 +31,15 @@ begin
   assign Fflow = subtraction ? ~adder_cout : adder_cout;
 end
 
+wire [31:0] mult_out_hi;
+wire [31:0] mult_out_lo;
+multiplier mult(A, B, mult_out_hi, mult_out_lo);
+
 assign O =
   op == 3'b000 ? adder_out :
   op == 3'b001 ? adder_out :
+  op == 3'b010 ? mult_out_hi :
+  op == 3'b011 ? mult_out_lo :
   op == 3'b100 ? A & B :
   op == 3'b101 ? A | B :
   op == 3'b110 ? A ^ B :
diff --git a/verilog-src/alu/multiplier.v b/verilog-src/alu/multiplier.v
new file mode 100644
index 0000000..49a9a7b
--- /dev/null
+++ b/verilog-src/alu/multiplier.v
@@ -0,0 +1,12 @@
+module multiplier(
+  input [31:0] A,
+  input [31:0] B,
+  output [31:0] O_hi,
+  output [31:0] O_lo
+);
+
+wire [63:0] O = A * B;
+assign O_lo = O[31:0];
+assign O_hi = O[63:32];
+
+endmodule