fox32-hw/verilog-src/alu/carry_select_block.v

module carry_select_block#(
  parameter N = 4
) (
  input [N-1:0] A,
  input [N-1:0] B,
  input Cin,
  output [N-1:0] O,
  output Cout
);

// Case for Cin = 0
wire [N-1:0] O_C0;
wire [N-1:0] O_C1;
wire [N:1] carry0;
wire [N:1] carry1;

fa fa00(A[0], B[0], 0, O_C0[0], carry0[1]);
fa fa10(A[0], B[0], 1, O_C1[0], carry1[1]);
genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
  fa fa0i(A[i], B[i], carry0[i], O_C0[i], carry0[i+1]);
  fa fa1i(A[i], B[i], carry1[i], O_C1[i], carry1[i+1]);
end

assign O = Cin == 0 ? O_C0 : O_C1;
assign Cout = Cin == 0 ? carry0[N] : carry1[N];

endmodule