fox32-hw/verilog-src/alu/fa.v

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2024-01-12 13:44:33 +01:00
// One bit full-adder
module fa(input A, input B, input Cin, output O, output Cout);
assign O = A ^ B ^ Cin;
assign Cout = (A & B) | (B & Cin) | (Cin & A);
endmodule