fox32-hw/verilog-src/alu/carry_select_block.v

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2024-01-12 13:44:33 +01:00
module carry_select_block#(
parameter N = 4
) (
input [N-1:0] A,
input [N-1:0] B,
input Cin,
output [N-1:0] O,
output Cout
);
// Case for Cin = 0
wire [N-1:0] O_C0;
wire Cout_C0;
begin
wire [N-1:1] carry;
fa fa0(A[0], B[0], 0, O_C0[0], carry[1]);
genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
fa fai(A[i], B[i], carry[i], O_C0[i], carry[i+1]);
end
assign Cout_C0 = carry[N-1];
end
// Case for Cin = 1
wire [N-1:0] O_C1;
wire Cout_C1;
begin
wire [N-1:1] carry;
fa fa0(A[0], B[0], 1, O_C1[0], carry[1]);
genvar i; for (i = 1; i <= N - 1; i = i + 1) begin
fa fai(A[i], B[i], carry[i], O_C1[i], carry[i+1]);
end
assign Cout_C1 = carry[N-1];
end
assign O = Cin == 0 ? O_C0 : O_C1;
assign Cout = Cin == 0 ? Cout_C0 : Cout_C1;
endmodule