369 lines
12 KiB
Python
Executable File
369 lines
12 KiB
Python
Executable File
#!/usr/bin/env python3
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# RISC-V assembly to fox32 translator
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import argparse
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import re
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class Emitter:
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"""
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The Emitter class emits fox32 assembly code.
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"""
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def __init__(self, filename):
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self.filename = filename
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self.f = open(filename, 'w')
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def write(self, line):
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self.f.write(line + '\n')
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@staticmethod
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def _adjust_label(label):
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"""
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Adjust a label to the requirements of fox32asm
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"""
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l = label.replace('.', '_')
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if l.startswith('_'):
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return 'U' + l[1:]
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return l
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@staticmethod
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def _adjust_operand(op):
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"""
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Adjust an operand to the requirements of fox32asm
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"""
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if re.fullmatch(r'-?[0-9]x?[0-9a-fA-F]*', op):
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return f'{int(op, 0) & 0xffffffff:#x}'
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return op
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def insn(self, operation, *operands):
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"""
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Emit an instruction
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"""
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line = '\t' + operation
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if operands:
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line += '\t' + ', '.join([self._adjust_operand(op) for op in operands])
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self.write(line)
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def include(self, filename):
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"""
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Emit an #include directive
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"""
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self.write(f'#include "{filename}"')
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def comment(self, line):
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"""
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Emit a comment
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"""
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self.write(f'; {line}')
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def label(self, label):
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"""
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Emit a label definition
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"""
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self.write(self._adjust_label(label) + ':')
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def data(self, *data, size=32):
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"""
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Emit data
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"""
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for d in data:
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self.write(f'data.{size} {self._adjust_label(self._adjust_operand(d))}')
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def zero(self, *data):
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"""
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Emit zeros
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"""
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for d in data:
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self.write(f'data.fill 0, {d}')
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def strz(self, *data):
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"""
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Emit null-terminated string
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"""
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for d in data:
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self.write(f'data.strz \"{d}\"')
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def nop(self):
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"""
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Emit a nop instruction
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"""
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self.insn('nop')
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def jump(self, label, condition=''):
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"""
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Emit a jump to a label, optionally with a condition code
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"""
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label = self._adjust_label(label)
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if condition:
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self.insn(f'{condition} rjmp', label)
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else:
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self.insn('rjmp', label)
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def jump_reg(self, reg):
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"""
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Emit a jump to a register
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"""
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self.insn('jmp', reg)
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def mov(self, dest, source, size=32):
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"""
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Emit a mov instruction
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"""
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self.insn(f'movz.{size}', dest, source)
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def store(self, rmem, rval, size=32):
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"""
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Emit a mov instruction that performs a memory store
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"""
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self.mov(f'[{rmem}]', rval, size)
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def load(self, rmem, rval, size=32):
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"""
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Emit a mov instruction that performs a memory load
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"""
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self.mov(rval, f'[{rmem}]', size)
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def rta(self, dest, source):
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"""
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Emit an rta instruction
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"""
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source = self._adjust_label(source)
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self.insn(f'rta', dest, source)
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def halt(self):
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"""
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Emit an halt instruction
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"""
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self.insn('halt')
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class Converter:
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"""
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This class converts RISC-V assembly code to fox32 assembly code
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"""
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def __init__(self, input, output, *, debug=False, start_file='start.asm', additional_includes=[]):
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self.input_file = open(input, 'r')
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self.e = Emitter(output)
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self.debug = debug
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self.start_file = start_file
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self.additional_includes = additional_includes
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self.xregs = [f'x{n}' for n in range(32)]
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self.regs = ['zero', 'ra', 'sp', 'gp', 'tp']
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self.regs += [f't{n}' for n in range(3)]
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self.regs += [f's{n}' for n in range(2)]
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self.regs += [f'a{n}' for n in range(8)]
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self.regs += [f's{n}' for n in range(2, 12)]
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self.regs += [f't{n}' for n in range(3, 7)]
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self.regidx = { r: i for i, r in enumerate(self.regs) }
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self.xregidx = { r: i for i, r in enumerate(self.xregs) }
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self.tmp = 'rfp' # temporary register
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self.branches = ['bge', 'bgeu', 'bgt', 'bgtu', 'blt', 'bltu', 'ble', 'bleu', 'bne', 'bneu', 'beq']
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self.label_gen = iter(range(1000000))
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def unique_label(self):
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return f'rv2fox_{(next(self.label_gen))}'
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@staticmethod
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def ldst_to_size(insn):
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size_map = {
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'lb': 8, 'lh': 16, 'lw': 32,
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'lbu': 8, 'lhu': 16,
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'sb': 8, 'sh': 16, 'sw': 32,
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}
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if insn in size_map:
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return size_map[insn]
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def ldst(self, insn, rval, rbase, offset):
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size = self.ldst_to_size(insn)
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if int(offset, 0) != 0:
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self.e.mov(self.tmp, rbase)
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self.e.insn('add', self.tmp, offset)
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rmem = self.tmp
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else:
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rmem = rbase
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if insn.startswith('s'):
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self.e.store(rmem, rval, size)
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else:
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self.e.load(rmem, rval, size)
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def convert_directive(self, line):
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if line in ['text', 'data']:
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pass # ignore
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elif m := re.fullmatch(r'word\s+([^\s]+)', line):
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self.e.data(*m.groups())
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elif m := re.fullmatch(r'half\s+([^\s]+)', line):
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self.e.data(*m.groups(), size=16)
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elif m := re.fullmatch(r'byte\s+([^\s]+)', line):
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self.e.data(*m.groups(), size=8)
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elif m := re.fullmatch(r'4byte\s+([^\s]+)', line):
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self.e.data(*m.groups())
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elif m := re.fullmatch(r'zero\s+([^\s]+)', line):
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self.e.zero(*m.groups())
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elif m := re.fullmatch(r'string\s+\"(.*)\"', line):
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self.e.strz(*m.groups())
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elif m := re.fullmatch(r'asciz\s+\"(.*)\"', line):
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self.e.strz(*m.groups())
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elif m := re.match(r'set\s([^,]*),', line):
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self.e.label(*m.groups())
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def reg(self, reg):
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"""
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Convert a RISC-V register to a fox32 register
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"""
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if reg == 'sp':
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return 'rsp'
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elif reg == 'zero':
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return f'0';
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elif reg in self.regidx:
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return f'r{self.regidx[reg]}'
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elif reg in self.xregidx:
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return f'r{self.xregidx[reg]}'
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else:
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raise Exception(f'Unknown register {reg}')
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@staticmethod
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def convert_arithmetic_op(op):
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if op in ['add', 'addi']: return 'add'
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if op in ['sub', 'subi']: return 'sub'
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if op in ['mul']: return 'mul'
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if op in ['div']: return 'idiv'
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if op in ['divu']: return 'div'
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if op in ['rem']: return 'irem'
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if op in ['remu']: return 'rem'
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if op in ['and', 'andi']: return 'and'
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if op in ['or', 'ori']: return 'or'
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if op in ['xor', 'xori']: return 'xor'
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if op in ['sll', 'slli']: return 'sla'
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if op in ['srl', 'srli']: return 'srl'
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else:
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raise Exception(f'Unknown op {op}')
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@staticmethod
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def convert_condition(op):
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if op in ['blt', 'bltu']: return 'iflt', False
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if op in ['bne', 'bnez']: return 'ifnz', False
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if op in ['beq', 'beqz']: return 'ifz', False
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if op in ['ble', 'bleu']: return 'ifgt', True
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if op in ['bge', 'bgeu']: return 'ifgteq', False
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if op in ['bgt', 'bgtu']: return 'ifgt', False
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def convert_branch(self, insn, rs1, rs2, label):
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cond, reverse = self.convert_condition(insn)
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if reverse:
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rs1, rs2 = rs2, rs1
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self.e.insn('cmp', self.reg(rs1), self.reg(rs2))
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self.e.jump(label, cond)
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def convert_branch_imm(self, insn, rs, label, imm):
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cond, reverse = self.convert_condition(insn)
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if reverse:
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rs1, rs2 = rs2, rs1
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self.e.insn('cmp', self.reg(rs), str(imm))
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self.e.jump(label, cond)
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@staticmethod
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def iter_operands(operands):
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if operands:
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for op in operands.split(','):
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op = op.strip()
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if op != '':
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yield op
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def convert_insn(self, insn, operands=None):
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tmp = self.tmp
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operands = list(self.iter_operands(operands))
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if insn == 'nop':
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self.e.nop()
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elif insn in ['addi', 'subi', 'div', 'rem', 'andi', 'ori', 'xori', 'slli', 'srli']:
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rd, rs, imm = operands
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op = self.convert_arithmetic_op(insn)
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if rd == rs:
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self.e.insn(op, self.reg(rd), imm)
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else:
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self.e.mov(tmp, self.reg(rs))
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self.e.insn(op, tmp, imm)
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self.e.mov(self.reg(rd), tmp)
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elif insn in ['add', 'sub', 'mul', 'divu', 'remu', 'and', 'or', 'nor', 'xor', 'sll', 'srl']:
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rd, rs1, rs2 = operands
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if rd == rs1:
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op = self.convert_arithmetic_op(insn)
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self.e.insn(op, self.reg(rd), self.reg(rs2))
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else:
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op = self.convert_arithmetic_op(insn)
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self.e.mov(tmp, self.reg(rs1))
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self.e.insn(op, tmp, self.reg(rs2))
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self.e.mov(self.reg(rd), tmp)
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elif insn in ['sw', 'lw', 'sh', 'lh', 'lhu', 'sb', 'lb', 'lbu']:
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rval, address = operands
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offset, rbase = re.fullmatch(r'(-?[0-9]+)\(([a-z0-9]+)\)', address).groups()
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self.ldst(insn, self.reg(rval), self.reg(rbase), offset)
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elif insn in ['j']:
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self.e.jump(*operands)
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elif insn in ['jr']:
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self.e.jump_reg(self.reg(*operands))
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elif insn in ['ret']:
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self.e.jump_reg(self.reg('ra'))
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elif insn in ['lla']:
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rd, label = operands
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self.e.rta(self.reg(rd), label)
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elif insn in ['mv']:
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rd, rs = operands
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self.e.mov(self.reg(rd), self.reg(rs))
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elif insn in ['call']:
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label = self.unique_label()
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self.e.mov(self.reg('ra'), label)
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self.e.jump(*operands)
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self.e.label(label)
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elif insn in self.branches:
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self.convert_branch(insn, *operands)
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elif insn in ['bnez']:
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self.convert_branch_imm(insn, *operands, 0)
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elif insn in ['li']:
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rd, imm = operands
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self.e.mov(self.reg(rd), imm)
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elif insn in ['lui']:
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rd, imm = operands
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self.e.mov(self.reg(rd), str(int(imm, 0) << 12))
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elif insn == 'wfi':
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self.e.halt()
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else:
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raise Exception(f'Unknown instruction {insn} {operands}')
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def convert(self):
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self.e.comment(f'Generated with rv2fox')
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self.e.include(self.start_file)
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for file in self.additional_includes:
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self.e.include(file)
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for i, line in enumerate(self.input_file):
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num = i + 1
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line = line.strip()
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if self.debug:
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self.e.write(f'\t; {line}')
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if line == '' or re.fullmatch(r'#.*', line):
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pass
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elif re.fullmatch(r'\.[a-z0-9]+.*', line):
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self.convert_directive(line[1:])
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elif m := re.fullmatch(r'([a-zA-Z0-9_.]+):', line):
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self.e.label(*m.groups())
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elif m := re.fullmatch(r'([a-z]+)', line) or \
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re.fullmatch(r'([a-z]+)\s+([^\s].*)', line):
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self.convert_insn(*m.groups())
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else:
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raise Exception(f'Unknown line: {line}')
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if __name__ == '__main__':
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parser = argparse.ArgumentParser(description='Convert RISC-V assembly to fox32 assembly')
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parser.add_argument('input', help='RISC-V input')
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parser.add_argument('-o', '--output', help='fox32 output')
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parser.add_argument('--debug', help='produce verbose output to allow debugging this tool', action='store_true')
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args = parser.parse_args()
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c = Converter(args.input, args.output, debug=args.debug)
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c.convert()
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