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rv2fox: Implement support for x0-x31 registers

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Ry 2023-02-05 16:42:17 -08:00
parent a8e199a763
commit fd6b39c0b7
1 changed files with 4 additions and 1 deletions
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gcc/rv2fox
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@ -121,12 +121,13 @@ class Converter:
self.start_file = start_file self.start_file = start_file
self.additional_includes = additional_includes self.additional_includes = additional_includes
self.xregs = ['x{n}' for n in range(32)] # TODO: map all registers, consider calling conventions self.xregs = [f'x{n}' for n in range(32)]
self.regs = ['zero', 'ra', 'sp', 'gp', 'tp'] self.regs = ['zero', 'ra', 'sp', 'gp', 'tp']
self.regs += [f't{n}' for n in range(3)] self.regs += [f't{n}' for n in range(3)]
self.regs += [f's{n}' for n in range(2)] self.regs += [f's{n}' for n in range(2)]
self.regs += [f'a{n}' for n in range(8)] self.regs += [f'a{n}' for n in range(8)]
self.regidx = { r: i for i, r in enumerate(self.regs) } self.regidx = { r: i for i, r in enumerate(self.regs) }
self.xregidx = { r: i for i, r in enumerate(self.xregs) }
self.tmp = 'r0' # temporary register self.tmp = 'r0' # temporary register
self.branches = ['bge', 'blt', 'ble', 'bne'] self.branches = ['bge', 'blt', 'ble', 'bne']
@ -172,6 +173,8 @@ class Converter:
return 'rsp' return 'rsp'
elif reg in self.regidx: elif reg in self.regidx:
return f'r{self.regidx[reg]}' return f'r{self.regidx[reg]}'
elif reg in self.xregidx:
return f'r{self.xregidx[reg]}'
else: else:
raise Exception(f'Unknown register {reg}') raise Exception(f'Unknown register {reg}')