gcc: Import from the demos repo
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14
gcc/README.md
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14
gcc/README.md
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# Compiling C code for fox32
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How does this work?
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- GCC compiles your C code with `riscv*-gcc -S hello.c -march=rv32im -mabi=ilp32 -O2`
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- `rv2fox` converts the generated RISC-V assembly to fox32 assembly
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- `fox32asm` makes an FXF binary
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## TODO:
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- commandline argument passing
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- calls out of C, into the ROM
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- testcase sha256 program that hashes the ROM
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- rust support: `rustc --emit asm --target riscv32im-unknown-none-elf test.rs -O`
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1
gcc/fox32-c++
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1
gcc/fox32-c++
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fox32-compile
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1
gcc/fox32-cc
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1
gcc/fox32-cc
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fox32-compile
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1
gcc/fox32-clang
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1
gcc/fox32-clang
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fox32-compile
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1
gcc/fox32-clang++
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gcc/fox32-clang++
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fox32-compile
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170
gcc/fox32-compile
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170
gcc/fox32-compile
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#!/usr/bin/env python3
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# fox32-compile - fox32 compiler driver/wrapper
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import argparse, sys, subprocess, os, re, shutil
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def run(command_line):
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print(f"Running command: {command_line}")
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if code := subprocess.run(command_line).returncode:
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sys.stderr.write(f"Command failed (exit status {code}): {command_line})\n")
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sys.exit(1)
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class Flavor:
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"""
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Compiler flavor base class. The compiler flavor determines where we look
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for the compiler and how we invoke it.
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"""
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@classmethod
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def command_names(self):
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raise Exception(f"Please implement command_names() in class {self.__name__}")
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@classmethod
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def invoke(self, command, c_file, s_file):
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raise Exception(f"Please implement invoke() in class {self.__name__}")
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class GCC(Flavor):
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basename = 'gcc'
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def prefixes():
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for bits in ['32', '64']:
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yield f'riscv{bits}-linux-gnu-'
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@classmethod
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def command_names(self):
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for p in self.prefixes():
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yield p + self.basename
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@classmethod
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def invoke(self, command, c_file, s_file):
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run([command, '-march=rv32im', '-mabi=ilp32', '-Os', '-S', c_file, '-o', s_file])
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class GPlusPlus(GCC):
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basename = 'g++'
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class Clang(Flavor):
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basename = 'clang'
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@classmethod
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def command_names(self):
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yield self.basename
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@classmethod
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def invoke(self, command, c_file, s_file):
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run([command, '-target', 'riscv32', '-Os', '-S', c_file, '-o', s_file])
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class ClangPlusPlus(Clang):
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basename = 'clang++'
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class RustC(Flavor):
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pass # TODO
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class Driver:
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"""
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Main compiler driver. It finds the right compiler and invokes it
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"""
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def __init__(self, argv0, args):
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self.basename = os.path.basename(argv0)
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self.args = args
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self.flavors = self.determine_flavors()
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self.c_files, self.asm_files = self.classify_inputs(args.INPUT)
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self.output = self.determine_output()
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self.rv2fox = os.path.dirname(argv0) + '/rv2fox'
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self.fox32asm = 'fox32asm'
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@staticmethod
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def classify_inputs(inputs):
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c = []
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asm = []
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for file in inputs:
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if file.endswith('.c'):
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c.append(file)
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elif file.endswith('.asm'):
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asm.append(file)
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else:
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sys.stderr.write(f"Can't classify filename '{file}'\n")
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sys.exit(1)
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if not c:
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sys.stderr.write(f"No C/C++ input file provided. Can't continue.\n")
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sys.exit(1)
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if len(c) > 1:
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sys.stderr.write(f"More than one C/C++ input file specified. This is currently not supported.\n")
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sys.exit(1)
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if asm:
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sys.stderr.write(f"ASM files specified. This is not yet supported.\n")
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sys.exit(1)
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return c, asm
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def determine_output(self):
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if self.args.output:
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out = self.args.output
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if not out.endswith('.fxf') and not out.endswith('.bin'):
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sys.stderr.write(f"Invalid output filename '{out}'. Must end with .fxf or .bin\n")
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sys.exit(1)
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return out
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file = self.c_files[0]
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if m := re.fullmatch(r'(.*)\.\w+', file):
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return m.groups()[0] + '.fxf'
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@staticmethod
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def find_flavor(name):
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match name:
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case 'gcc': return [GCC]
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case 'g++': return [GPlusPlus]
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case 'clang': return [Clang]
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case 'clang++': return [ClangPlusPlus]
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case 'cc': return [GCC, Clang]
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case 'c++': return [GPlusPlus, ClangPlusPlus]
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def determine_flavors(self):
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if self.args.flavor:
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if not (flavors := self.find_flavor(self.args.flavor)):
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sys.stderr.write(f"Specified flavor '{self.args.flavor}' is not supported.\n")
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sys.exit(1)
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return flavors
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m = re.fullmatch(r'fox32-(.*)', self.basename)
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if not m or not (flavors := self.find_flavor(*m.groups())):
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sys.stderr.write(f"Program was invoked as {self.basename}, can't determine flavor.\n")
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sys.stderr.write(f"Please use e.g. '--flavor gcc' or invoke fox32-gcc\n")
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sys.exit(1)
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return flavors
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def determine_command(self):
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for flavor in self.flavors:
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for command_name in flavor.command_names():
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if shutil.which(command_name):
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return flavor, command_name
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sys.stderr.write(f"No suitable compiler found.\n")
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sys.exit(1)
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def compile(self):
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flavor, command = self.determine_command()
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main_asm_files = []
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for c_file in self.c_files:
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s_file = c_file + '.tmp.s'
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asm_file = c_file + '.tmp.asm'
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flavor.invoke(command, c_file, s_file)
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run([self.rv2fox, s_file, '-o', asm_file])
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main_asm_files.append(asm_file)
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command_line = [self.fox32asm, main_asm_files[0], self.output]
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if self.args.start_file:
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command_line += ['--start-file', self.args.start_file]
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run(command_line)
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if __name__ == '__main__':
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parser = argparse.ArgumentParser(description='fox32 compiler driver')
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parser.add_argument('INPUT', nargs='+', help='Inputs: .c/.cpp and .asm files')
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parser.add_argument('--output', '-o', help='Output file (.fxf or .bin)')
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parser.add_argument('--flavor', help='Flavor, i.e. gcc, g++, clang, etc.')
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parser.add_argument('--start-file', help='Start file to use instead of start.asm')
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args = parser.parse_args()
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driver = Driver(sys.argv[0], args)
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driver.compile()
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1
gcc/fox32-g++
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1
gcc/fox32-g++
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fox32-compile
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1
gcc/fox32-gcc
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1
gcc/fox32-gcc
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fox32-compile
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305
gcc/rv2fox
Executable file
305
gcc/rv2fox
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#!/usr/bin/env python3
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# RISC-V assembly to fox32 translator
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import argparse
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import re
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class Emitter:
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"""
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The Emitter class emits fox32 assembly code.
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"""
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def __init__(self, filename):
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self.filename = filename
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self.f = open(filename, 'w')
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def write(self, line):
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self.f.write(line + '\n')
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@staticmethod
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def _adjust_label(label):
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"""
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Adjust a label to the requirements of fox32asm
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"""
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l = label.replace('.', '_')
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if l.startswith('_'):
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return 'U' + l[1:]
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return l
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@staticmethod
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def _adjust_operand(op):
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"""
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Adjust an operand to the requirements of fox32asm
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"""
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if re.fullmatch(r'-?[0-9]x?[0-9a-fA-F]*', op):
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return f'{int(op, 0) & 0xffffffff:#x}'
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return op
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def insn(self, operation, *operands):
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"""
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Emit an instruction
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"""
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line = '\t' + operation
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if operands:
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line += '\t' + ', '.join([self._adjust_operand(op) for op in operands])
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self.write(line)
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def include(self, filename):
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"""
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Emit an #include directive
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"""
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self.write(f'#include "{filename}"')
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def comment(self, line):
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"""
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Emit a comment
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"""
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self.write(f'; {line}')
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def label(self, label):
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"""
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Emit a label definition
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"""
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self.write(self._adjust_label(label) + ':')
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def data(self, *data, size=32):
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"""
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Emit data
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"""
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for d in data:
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self.write(f'data.{size} {d}')
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def nop(self):
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"""
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Emit a nop instruction
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"""
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self.insn('nop')
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def jump(self, label, condition=''):
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"""
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Emit a jump to a label, optionally with a condition code
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"""
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label = self._adjust_label(label)
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if condition:
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self.insn(f'{condition} rjmp', label)
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else:
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self.insn('rjmp', label)
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def jump_reg(self, reg):
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"""
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Emit a jump to a register
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"""
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self.insn('jmp', reg)
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def mov(self, dest, source, size=32):
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"""
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Emit a mov instruction
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"""
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self.insn(f'movz.{size}', dest, source)
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def store(self, rmem, rval, size=32):
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"""
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Emit a mov instruction that performs a memory store
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"""
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self.mov(f'[{rmem}]', rval, size)
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def load(self, rmem, rval, size=32):
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"""
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Emit a mov instruction that performs a memory load
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"""
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self.mov(rval, f'[{rmem}]', size)
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class Converter:
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"""
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This class converts RISC-V assembly code to fox32 assembly code
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"""
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def __init__(self, input, output, *, debug=False, start_file='start.asm', additional_includes=[]):
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self.input_file = open(input, 'r')
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self.e = Emitter(output)
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self.debug = debug
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self.start_file = start_file
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self.additional_includes = additional_includes
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self.xregs = ['x{n}' for n in range(32)] # TODO: map all registers, consider calling conventions
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self.regs = ['zero', 'ra', 'sp', 'gp', 'tp']
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self.regs += [f't{n}' for n in range(3)]
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self.regs += [f's{n}' for n in range(2)]
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self.regs += [f'a{n}' for n in range(8)]
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self.regidx = { r: i for i, r in enumerate(self.regs) }
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self.tmp = 'r0' # temporary register
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self.branches = ['bge', 'blt', 'ble', 'bne']
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self.label_gen = iter(range(1000000))
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def unique_label(self):
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return f'rv2fox_{(next(self.label_gen))}'
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@staticmethod
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def ldst_to_size(insn):
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size_map = {
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'lb': 8, 'lh': 16, 'lw': 32,
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'sb': 8, 'sh': 16, 'sw': 32,
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}
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if insn in size_map:
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return size_map[insn]
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def ldst(self, insn, rval, rbase, offset):
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size = self.ldst_to_size(insn)
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if int(offset, 0) != 0:
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self.e.mov(self.tmp, rbase)
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self.e.insn('add', self.tmp, offset)
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rmem = self.tmp
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else:
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rmem = rbase
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if insn.startswith('s'):
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self.e.store(rmem, rval, size)
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else:
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self.e.load(rmem, rval, size)
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def convert_directive(self, line):
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if line in ['text', 'data']:
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pass # ignore
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elif m := re.fullmatch(r'word\s+([^\s]+)', line):
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self.e.data(*m.groups())
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def reg(self, reg):
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"""
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Convert a RISC-V register to a fox32 register
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"""
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if reg == 'sp':
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return 'rsp'
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elif reg in self.regidx:
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return f'r{self.regidx[reg]}'
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else:
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raise Exception(f'Unknown register {reg}')
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@staticmethod
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def convert_arithmetic_op(op):
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if op in ['add', 'addi']: return 'add'
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if op in ['sll', 'slli']: return 'sla'
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else:
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raise Exception(f'Unknown op {op}')
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@staticmethod
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def convert_condition(op):
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if op in ['blt']: return 'iflt', False
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if op in ['bne', 'bnez']: return 'ifnz', False
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if op in ['ble']: return 'ifgt', True
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def convert_branch(self, insn, rs1, rs2, label):
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cond, reverse = self.convert_condition(insn)
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if reverse:
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rs1, rs2 = rs2, rs1
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self.e.insn('cmp', self.reg(rs1), self.reg(rs2))
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self.e.jump(label, cond)
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def convert_branch_imm(self, insn, rs, label, imm):
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cond, reverse = self.convert_condition(insn)
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if reverse:
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rs1, rs2 = rs2, rs1
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self.e.insn('cmp', self.reg(rs), str(imm))
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self.e.jump(label, cond)
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@staticmethod
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def iter_operands(operands):
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if operands:
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for op in operands.split(','):
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op = op.strip()
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if op != '':
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yield op
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def convert_insn(self, insn, operands=None):
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tmp = self.tmp
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operands = list(self.iter_operands(operands))
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if insn == 'nop':
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self.e.nop()
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elif insn in ['addi', 'slli']:
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rd, rs, imm = operands
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op = self.convert_arithmetic_op(insn)
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if rd == rs:
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self.e.insn(op, self.reg(rd), imm)
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else:
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self.e.mov(tmp, self.reg(rs))
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self.e.insn(op, tmp, imm)
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self.e.mov(self.reg(rd), tmp)
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elif insn in ['add']:
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rd, rs1, rs2 = operands
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if rd == rs1:
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op = self.convert_arithmetic_op(insn)
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self.e.insn(op, self.reg(rd), self.reg(rs2))
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else:
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op = self.convert_arithmetic_op(insn)
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self.e.mov(tmp, self.reg(rs1))
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self.e.insn(op, tmp, self.reg(rs2))
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self.e.mov(self.reg(rd), tmp)
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elif insn in ['sw', 'lw']:
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rval, address = operands
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offset, rbase = re.fullmatch(r'(-?[0-9]+)\(([a-z0-9]+)\)', address).groups()
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self.ldst(insn, self.reg(rval), self.reg(rbase), offset)
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elif insn in ['j']:
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self.e.jump(*operands)
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elif insn in ['jr']:
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self.e.jump_reg(self.reg(*operands))
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elif insn in ['ret']:
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self.e.jump_reg(self.reg('ra'))
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elif insn in ['lla']:
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rd, label = operands
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self.e.rta(self.reg(rd), label)
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elif insn in ['mv']:
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rd, rs = operands
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self.e.mov(self.reg(rd), self.reg(rs))
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elif insn in ['call']:
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label = self.unique_label()
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self.e.mov(self.reg('ra'), label)
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self.e.jump(*operands)
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self.e.label(label)
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elif insn in self.branches:
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||||
self.convert_branch(insn, *operands)
|
||||
elif insn in ['bnez']:
|
||||
self.convert_branch_imm(insn, *operands, 0)
|
||||
elif insn in ['li']:
|
||||
rd, imm = operands
|
||||
self.e.mov(self.reg(rd), imm)
|
||||
elif insn in ['lui']:
|
||||
rd, imm = operands
|
||||
self.e.mov(self.reg(rd), str(int(imm, 0) << 12))
|
||||
else:
|
||||
raise Exception(f'Unknown instruction {insn} {operands}')
|
||||
|
||||
def convert(self):
|
||||
self.e.comment(f'Generated with rv2fox')
|
||||
|
||||
self.e.include(self.start_file)
|
||||
for file in self.additional_includes:
|
||||
self.e.include(file)
|
||||
|
||||
for i, line in enumerate(self.input_file):
|
||||
num = i + 1
|
||||
line = line.strip()
|
||||
|
||||
if self.debug:
|
||||
self.e.write(f'\t; {line}')
|
||||
|
||||
if line == '' or re.fullmatch(r'#.*', line):
|
||||
pass
|
||||
elif re.fullmatch(r'\.[a-z]+.*', line):
|
||||
self.convert_directive(line[1:])
|
||||
elif m := re.fullmatch(r'([a-zA-Z0-9_.]+):', line):
|
||||
self.e.label(*m.groups())
|
||||
elif m := re.fullmatch(r'([a-z]+)', line) or \
|
||||
re.fullmatch(r'([a-z]+)\s+([^\s].*)', line):
|
||||
self.convert_insn(*m.groups())
|
||||
else:
|
||||
raise Exception(f'Unknown line: {line}')
|
||||
|
||||
if __name__ == '__main__':
|
||||
parser = argparse.ArgumentParser(description='Convert RISC-V assembly to fox32 assembly')
|
||||
parser.add_argument('input', help='RISC-V input')
|
||||
parser.add_argument('-o', '--output', help='fox32 output')
|
||||
parser.add_argument('--debug', help='produce verbose output to allow debugging this tool', action='store_true')
|
||||
args = parser.parse_args()
|
||||
c = Converter(args.input, args.output, debug=args.debug)
|
||||
c.convert()
|
||||
Loading…
Reference in New Issue
Block a user